10AX115U3F45E2LG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115U3F45E2LG sa pamamagitan ng Intel at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115U3F45E2LG - Arria 10 GX FPGA 1150K LE | Intel | 1932-FCBGA
10AX115U3F45E2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115U3F45E2LG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 GX | — |
| Family | Arria 10 | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Embedded Memory Bits | 68,857,856 | 68,857,856 (≈ 52.99 Mbit) |
| User I/O Count | 480 | — |
| Speed Grade | U3 (medium-performance, transceiver-focused) | -2 (E2 commercial/extended) |
| Package Code | F45 (45 × 45 mm FCBGA) | — |
| Package Type | 1932-ball FCBGA (Flip-Chip BGA) | — |
| Process Technology | 20 nm TSMC | — |
| Transceiver Data Rate | Up to 28.05 Gbps | — |
| DSP Blocks | Variable-precision, 1.5 TFLOPs FP32 | Variable-precision, hardened floating-point |
| PCIe Hard IP | Gen3 x8/x16 | — |
| Memory Interfaces | DDR4, DDR3, QDR IV, RLDRAM 3 | — |
| Temperature na Operasyon | 0C to +100C (Industrial, E2 grade) | Industrial (junction -40 °C to +100 °C) – device grade U |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Configuration Method | SRAM-based, loaded via JTAG / AS / PS | FPGA configuration via serial/parallel flash, JTAG |
| Tindminan RoHS | Compliant | — |
| Lead-Free / Halogen-Free | Yes / Yes | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard Memory Controllers | — | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Packhaging | — | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Process Node | — | 20 nm Tri-Gate (Intel) |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |