EP1810GC-35 vs EP1810JI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GC-35 sa pamamagitan ng Altera at EP1810JI-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GC-35 | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | — |
| Packhaging | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Bilang ng Pins | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Uri ng Pagpapasok | Through Hole | Through-Hole (J-lead) |
| Tindminan RoHS | Not applicable (legacy ceramic package) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |