EP1810GI-45 vs EP1810JC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810JC-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GI-45 EP1810JC-35
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type UV Erasable Programmable Logic Device (EPLD) UV-Erasable Complex PLD (UV PLD / CPLD)
Family Altera Classic EPLD —
Macrocells 24 —
Flip-Flops 48 —
Propagation Delay (tpd) 45 ns 35 ns (max)
Speed Grade -45 —
Technology CMOS —
Package Type Ceramic Pin Grid Array with UV window CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Bilang ng Pin 68 —
Uri ng Pagpapasok Through-Hole Surface Mount (J-Lead)
Programmable Yes (UV-erasable, electrically programmable) —
Tindminan RoHS Non-compliant (ceramic PGA) Compliant (per Altera listing)
Lead-Free No —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
Device Family — Classic EPLD (EP1810)
Number of Macrocells — 48
Maksimum na Taktiko ng Oras — [DATA_NEEDED: fmax for this speed grade]
Process Technology — CMOS
Supply Voltage (Vcc) — 5 V (nominal)
Maximum Supply Voltage — 5.25 V (per distributor listing)
Number of Terminals — 68
Terminal Form — J-Bend
Hanay ng Temperature na Operasyon — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Erasure Method — UV (quartz-windowed ceramic package)
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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