EP1810GI-45 vs EP1810JC-35 比較
詳細並排比較 EP1810GI-45 由 Altera 與 EP1810JC-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GI-45 | EP1810JC-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | — |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| Speed Grade | -45 | — |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| 腳位數 | 68 | — |
| 安裝類型 | Through-Hole | Surface Mount (J-Lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 狀態 | Non-compliant (ceramic PGA) | Compliant (per Altera listing) |
| Lead-Free | No | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| 最大時脈頻率 | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 工作溫度範圍 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |