EP1810JC-35 vs EP1810JM-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-35 sa pamamagitan ng Intel at EP1810JM-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-35 | EP1810JM-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810) | Classic EPLD (EP1810 series) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max, -45 speed grade) |
| Maksimum na Taktiko ng Oras | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | JLCC-68 (ceramic J-leaded chip carrier) |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Hanay ng Temperature na Operasyon | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Tindminan RoHS | Compliant (per Altera listing) | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Uri ng Pagpapasok | Surface Mount (J-Lead) | Surface Mount (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-EPROM configuration |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| Bilang ng Pin | — | 68 |
| Temperature na Operasyon | — | -55 C to +125 C (military grade) |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |