EP1810LC-45 vs EP1810JC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-45 sa pamamagitan ng Rochester Electronics at EP1810JC-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-45 EP1810JC-35
Brand Rochester Electronics Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable Complex PLD (UV PLD / CPLD)
Usable Gates 900 —
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns 35 ns (max)
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) 5 V (nominal)
Process Technology 5 V CMOS EPROM CMOS
Packhaging 68-pin PLCC (J-lead) —
Temperature na Operasyon 0 °C to +70 °C (commercial) —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount (J-Lead)
Tindminan RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] Compliant (per Altera listing)
Lead-Free [DATA_NEEDED: lead-free finish] —
Device Family — Classic EPLD (EP1810)
Number of Macrocells — 48
Maksimum na Taktiko ng Oras — [DATA_NEEDED: fmax for this speed grade]
Maximum Supply Voltage — 5.25 V (per distributor listing)
Package Type — CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Number of Terminals — 68
Terminal Form — J-Bend
Hanay ng Temperature na Operasyon — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Erasure Method — UV (quartz-windowed ceramic package)
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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