EP1810LC-45 vs EP1810JC-35 比較
詳細並排比較 EP1810LC-45 由 Rochester Electronics 與 EP1810JC-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete
規格比較
| 參數 | EP1810LC-45 | EP1810JC-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | 5 V (nominal) |
| Process Technology | 5 V CMOS EPROM | CMOS |
| 封裝 | 68-pin PLCC (J-lead) | — |
| 工作溫度 | 0 °C to +70 °C (commercial) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (J-Lead) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of Rochester-sourced part] | Compliant (per Altera listing) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| 最大時脈頻率 | — | [DATA_NEEDED: fmax for this speed grade] |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 工作溫度範圍 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |