EP2AGX125DF25I3G vs EP2AGX45DF25I3G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGX125DF25I3G sa pamamagitan ng Intel at EP2AGX45DF25I3G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2AGX125DF25I3G - 118K LE Arria II GX FPGA, 3.75Gbps, FC-FBGA | Intel
EP2AGX125DF25I3G ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2AGX125DF25I3G | EP2AGX45DF25I3G |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Series | Arria II GX | — |
| Logic Elements | 118,143 | — |
| Embedded Memory | 8,315,904 bits | — |
| Number of I/O | 260 | — |
| Packhaging | 572-BGA, FCBGA (Flip-Chip FineLine BGA) | 572-ball FCBGA (HBGA) |
| Core Voltage | 0.9 V | — |
| Process Technology | 40 nm | — |
| Maximum Operating Frequency | 500 MHz | — |
| Transceivers | Up to 12 (3.75 Gbps per channel) | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Volte ng Pagbibigay | 0.9 V core | — |
| DSP Blocks | 18x18 multipliers | — |
| Level ng MSL | [DATA_NEEDED: MSL Level] | 3 |
| Tindminan RoHS | Compliant | Compliant |
| Family | — | Arria II GX |
| Logic Elements (LE) | — | 42,959 |
| Adaptive Logic Modules (ALM) | — | 17,715 |
| Embedded Memory Bits | — | 3,517,440 bits |
| Embedded Memory M9K Blocks | — | [DATA_NEEDED: M9K block count] |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: DSP block count] |
| Maximum User I/O Pins | — | 252 |
| Transceiver Channels | — | [DATA_NEEDED: MGT channel count] |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Package Dimensions | — | 25 mm x 25 mm |
| Hanay ng Temperature na Operasyon | — | -40C to +100C (Industrial) |
| Speed Grade | — | I3 |
| Process Node | — | 40 nm |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT] |
| Hard IP for PCIe | — | PCIe Gen1/Gen2 endpoints and root ports |
| Lead-Free | — | Yes |