EP610JI-30 vs EP610LI-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610JI-30 sa pamamagitan ng Altera at EP610LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610JI-30 EP610LI-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD (EP610) Classic EPLD
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 16 —
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Product Terms 160 160
Dedicated Inputs 4 4
I/O Pins 16 —
External Clocks 2 —
Volte ng Pagbibigay 5 V (single supply) 5 V
Process Technology CMOS CMOS
Packhaging CQCC28 (windowed ceramic JLCC, J-bend) 28-pin PLCC (windowed ceramic, 'LI')
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Temperature na Operasyon -40C to +85C (industrial, per EP610 family suffix convention) —
Uri ng Pagpapasok Surface Mount (JLCC) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free status] —
Series — EP610
Number of Macrocells — 16
Usable Gates — 300
Number of I/O Pins — 16
Total Inputs — 20
External Clock Inputs — 2
Maximum Propagation Delay — 35 ns (tpd)
Maximum Operating Frequency — 28.6 MHz (fmax)
Architecture — PAL-type (AND-OR array)
Hanay ng Temperature na Operasyon — [DATA_NEEDED: military/industrial operating temperature range]
Programming Technology — UV-erasable (EPROM)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita