EPC2L20N vs EPC2L120N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L20N sa pamamagitan ng Altera at EPC2L120N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2L20N | EPC2L120N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Fungsi | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Laki ng Memory | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Packhaging / Kaso | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Uri ng Pagpapasok | Surface Mount (J-Lead PLCC) | — |
| Bilang ng Pin | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| Level ng MSL | 3 (168 hours) | — |
| Tindminan RoHS | Compliant | unknown |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Packhaging | — | 84-pin PLCC (J-Lead) |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |