EPC2L20N vs EPC2L120N Karşılaştırma
Ayrıntılı yan yana karşılaştırma EPC2L20N tarafından Altera ve EPC2L120N tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EPC2L20N | EPC2L120N |
|---|---|---|
| Marka | Altera | Intel |
| Kategori | Memory ICs | FPGA & CPLD |
| Yaşam Döngüsü Durumu | NRND | Obsolete |
| Fonksiyon | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Bellek Boyutu | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Paket / Kas | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| İşletim Sıcaklığı | 0C to +70C (commercial) | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Montaj Türü | Surface Mount (J-Lead PLCC) | — |
| Pin Sayısı | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| MSL Seviyesi | 3 (168 hours) | — |
| RoHS Durumu | Compliant | unknown |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Paket | — | 84-pin PLCC (J-Lead) |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |