EPM5128JC vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family MAX 5000 —
Device Type EPLD / CPLD EPLD (Erasable PLD)
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns —
Logic Elements Programmable AND/OR/XOR array —
Supply Voltage (VCC) 5 V (typical) 5 V (typical, 4.75 V - 5.25 V range)
Bilang ng Pins 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 —
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) EPROM (UV-erasable window or OTP)
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer —
Temperature na Operasyon Commercial 0C to +70C [DATA_NEEDED: operating temperature grade]
Uri ng Pagpapasok Surface Mount (PLCC socket or solder) Surface Mount (socketed)
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM —
Tindminan RoHS [DATA_NEEDED: RoHS status - legacy part] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Family — MAX 5000
Macrocells — 64
Usable Gates — 1,250 (approx.)
Logic Array Inputs — 36
Logic Array Outputs — 64
Packhaging — 68-pin PLCC (JEDEC)
I/O Logic Level — TTL / CMOS compatible
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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