EPM5128JC vs EPM5064JC 比較
詳細並排比較 EPM5128JC 由 Altera 與 EPM5064JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128JC | EPM5064JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | EPLD (Erasable PLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V (typical, 4.75 V - 5.25 V range) |
| 腳位數 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | EPROM (UV-erasable window or OTP) |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 工作溫度 | Commercial 0C to +70C | [DATA_NEEDED: operating temperature grade] |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Surface Mount (socketed) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Family | — | MAX 5000 |
| Macrocells | — | 64 |
| Usable Gates | — | 1,250 (approx.) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 封裝 | — | 68-pin PLCC (JEDEC) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |