EPM5192JC68 vs EPM5192JC-ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC68 sa pamamagitan ng Altera at EPM5192JC-ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC68 EPM5192JC-ES
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 5000 MAX 5000
Product Type EPLD (Erasable Programmable Logic Device) —
Logic Elements / Macrocells 192 macrocells —
User I/O Pins 76 [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Bilang ng Pins 68 —
Package Type PLCC-68 (J-Lead) —
Temperature na Operasyon 0C to 70C (commercial, JC suffix) [DATA_NEEDED: operating temperature range for ES grade]
Volte ng Pagbibigay [DATA_NEEDED: VCC] [DATA_NEEDED: VCC nominal]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD] —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX] —
Configuration Memory UV-Erasable EPROM EPROM (UV-erasable, one-time programmable for JC-ES)
Programmable Interconnect Programmable Logic Array + Macrocells —
Dedicated Inputs 12 —
Clock Pins 4 dedicated —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Programming Tool MAX+PLUS II (legacy) —
Device Type — CPLD (EPLD)
Macrocells — 192
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
Packhaging — 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Technology — CMOS
Programming — Altera MAX+PLUS II or compatible programmer
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Note — Datasheet source: Altera MAX 5000 family document, 52 pages

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