EPM5192JC68 vs EPM5192JC-ES 比較
詳細並排比較 EPM5192JC68 由 Altera 與 EPM5192JC-ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC68 | EPM5192JC-ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Elements / Macrocells | 192 macrocells | — |
| User I/O Pins | 76 | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| 腳位數 | 68 | — |
| Package Type | PLCC-68 (J-Lead) | — |
| 工作溫度 | 0C to 70C (commercial, JC suffix) | [DATA_NEEDED: operating temperature range for ES grade] |
| 供應電壓 | [DATA_NEEDED: VCC] | [DATA_NEEDED: VCC nominal] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Configuration Memory | UV-Erasable EPROM | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Programmable Interconnect | Programmable Logic Array + Macrocells | — |
| Dedicated Inputs | 12 | — |
| Clock Pins | 4 dedicated | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Programming Tool | MAX+PLUS II (legacy) | — |
| Device Type | — | CPLD (EPLD) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| 封裝 | — | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |