EPM9560ARC208-10 vs EPM9560R1208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC208-10 sa pamamagitan ng Intel at EPM9560R1208-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560ARC208-10 | EPM9560R1208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000A (Multiple Array MatriX) | — |
| Programmable Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 gates | 6,000 |
| Macrocells | 560 macrocells | 560 |
| Logic Array Blocks | 35 LABs | 52 (typical for 560 macrocells) |
| User I/O Pins | 153 I/O | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 20 ns |
| Internal Frequency | 144.9 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Logic Family | CMOS | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP) | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Packhaging | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad | R-1208 (BGA-style fine-pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| Bilang ng Pin | 208 pins | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 212 |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM, third-generation MAX architecture |
| Architecture | — | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |