K4S641632K-UC75 vs K4S641632H-UC75 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng K4S641632K-UC75 sa pamamagitan ng Samsung Electro-Mechanics at K4S641632H-UC75 sa pamamagitan ng Samsung Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Samsung Electro-Mechanics
K4S641632K-UC75 - 64Mb SDRAM 4Mx16 3.3V 54-TSOP II | Samsung
K4S641632K-UC75 ✓ NakahandaSamsung Electronics
K4S641632H-UC75 - 64Mb H-die SDRAM 1M x 16 x 4 Banks | Samsung
K4S641632H-UC75 ObsoletePagsanggunian na paghahambing
| Parametro | K4S641632K-UC75 | K4S641632H-UC75 |
|---|---|---|
| Brand | Samsung Electro-Mechanics | Samsung Electronics |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Uri ng Memory | Synchronous DRAM (SDR SDRAM) | SDRAM (Synchronous DRAM) |
| Density | 64 Mbit (67,108,864 bits) | 64 Mb (67,108,864 bits) |
| Organisasyon | 4 banks x 1,048,576 words x 16 bits (4Mx16) | 1M x 16 bits x 4 Banks |
| Supply Voltage (VDD/VDDQ) | 3.3 V +/- 0.3 V | 3.3 V |
| Speed Grade | UC75 (133 MHz, CAS Latency 3, tCK = 7.5 ns) | — |
| Maksimum na Taktiko ng Oras | 133 MHz | — |
| CAS Latency (CL) | 2 or 3 (programmable) | — |
| Burst Length | 1, 2, 4, 8 or full page | 1, 2, 4, 8, Full Page |
| Refresh Cycles | 4096 (64 ms refresh interval) | — |
| Number of Banks | 4 | — |
| Address Multiplexing | Row: 12 bits, Column: 8 bits | Yes (RAS#, CAS# controlled) |
| Interface | 16-bit data bus, LVTTL-compatible | LVCMOS |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0C to +70C (Commercial) |
| Packhaging | 54-pin TSOP-II | — |
| Package Outline | 10.16 mm x 22.22 mm, 0.8 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount (Tape & Reel) | — |
| Process Technology | Samsung high-performance CMOS | Samsung high-performance CMOS |
| Tindminan RoHS | Compliant | — |
| Clock Frequency | — | 133 MHz |
| Max Operating Current | — | 135 mA |
| Package Type | — | 54-pin TSOP-II |
| Lead Finish | — | Pb-Free (RoHS compliant) |
| Bank Architecture | — | 4 Banks |
| Burst Type | — | Sequential or Interleave |
| Refresh | — | Auto-Refresh and Self-Refresh |
| Data Width | — | 16 bits |