EP1810GM883 vs EP1810JC-25 比較
詳細並排比較 EP1810GM883 由 Altera 與 EP1810JC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883 | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD (EP1810 series) | Altera/Intel Classic EPLD (EP1810 series) |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Dedicated Inputs | 12 | 12 |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | — |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| 封裝 | 68-Pin Ceramic Pin Grid Array (PGA) | 28-pin ceramic DIP (J) with quartz window |
| 工作溫度 | -55C to +125C (MIL-STD-883 Class B) | -40 °C to 85 °C (industrial, per distributor listings) |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| 安裝類型 | Through-Hole (PGA socket) | Through-hole |
| RoHS 狀態 | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| Erasure Method | — | UV light (windowed package) |
| 生命週期狀態 | — | NRND (Not Recommended for New Designs) |