EP1810JC-35 vs EP1810GM883 比較
詳細並排比較 EP1810JC-35 由 Intel 與 EP1810GM883 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-35 | EP1810GM883 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | UV-Erasable Programmable Logic Device (EPLD) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max) |
| 最大時脈頻率 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS, UV-erasable |
| Supply Voltage (Vcc) | 5 V (nominal) | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作溫度範圍 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 狀態 | Compliant (per Altera listing) | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 安裝類型 | Surface Mount (J-Lead) | Through-Hole (PGA socket) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Family | — | Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| 封裝 | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| 工作溫度 | — | -55C to +125C (MIL-STD-883 Class B) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |