EP610LI-15 vs EP610IDC-15 比較
詳細並排比較 EP610LI-15 由 Altera 與 EP610IDC-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610LI-15 | EP610IDC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 最後購買 |
| Device Family | Classic EPLD EP610 | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Counter Frequency (fCNT) | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| 工作溫度 | 0 C to +70 C (commercial, "I" grade) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable / OTP |
| 封裝 | 24-pin ceramic DIP, side-brazed, windowed (DIP-24) | 24-pin CerDIP (ceramic DIP) |
| 腳位數 | 24 | — |
| Programming Method | UV erase + EPROM programmer | — |
| Logic Blocks | AND/OR array, 16 output macrocells | — |
| I/O Standard | TTL/CMOS compatible | — |
| 輸出類型 | 3-state | — |
| RoHS 狀態 | Non-compliant (ceramic DIP, SnPb finish typical) | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Manufacturer (current) | Rochester Electronics (authorized Altera legacy distributor) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| 安裝類型 | — | Through-hole |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |