EPM5032DM883B vs EPM5032DC20 比較
詳細並排比較 EPM5032DM883B 由 Altera 與 EPM5032DC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DM883B | EPM5032DC20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Classic EPLD) | — |
| Macrocells | 32 | 32 |
| Logic Elements | 32 macrocells (MAX architecture) | — |
| Technology | UV-erasable EPROM cell | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | 20 ns |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL-compatible I/O) | 5 V (4.75 V to 5.25 V) |
| 工作溫度 | MILITARY (per /883B screen) | [DATA_NEEDED: operating temperature range] |
| MIL-STD-883 Screening | Class B (DM/883B) | — |
| Package Type | WDIP-28 (ceramic DIP with quartz window) | — |
| 腳位數 | 28 | — |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Terminal Form | Through-Hole | — |
| Package Shape | RECTANGULAR | — |
| Programming Method | Programmer + UV erase | — |
| RoHS 狀態 | [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 16 (bidirectional) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS |
| 封裝 | — | 20-pin Ceramic DIP (DC) with UV window |