EPM5192JC-2 vs EPM5192JC68 比較
詳細並排比較 EPM5192JC-2 由 Altera 與 EPM5192JC68 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-2 | EPM5192JC68 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 76 |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | — |
| 最大時脈頻率 | 40 MHz | — |
| Process Technology | CMOS | — |
| 封裝 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements / Macrocells | — | 192 macrocells |
| 腳位數 | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| 工作溫度 | — | 0C to 70C (commercial, JC suffix) |
| 供應電壓 | — | [DATA_NEEDED: VCC] |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Configuration Memory | — | UV-Erasable EPROM |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |