H5AN8G6NAFR-RDC vs H5AN8G6NAFR-UHC 比較
詳細並排比較 H5AN8G6NAFR-RDC 由 SK hynix 與 H5AN8G6NAFR-UHC 由 SK hynix. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | H5AN8G6NAFR-RDC | H5AN8G6NAFR-UHC |
|---|---|---|
| 品牌 | SK hynix | SK hynix |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 記憶體類型 | DDR4 SDRAM | DDR4 SDRAM (CMOS) |
| Memory Density | 8 Gb | 8 Gbit |
| 組織 | 512M x 16 | 512M x 16 |
| 供應電壓 | 1.2 V | 1.2 V |
| 介面 | DDR4 (JEDEC-standard) | — |
| Access Mode | Multi Bank Page Burst | — |
| Package Code | TFBGA | — |
| Package Shape | Rectangular | — |
| Number of Terminals | 96 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Temperature Grade | OTHER (per Partstack listing) | — |
| Technology | CMOS | — |
| RoHS 狀態 | Compliant (Lead-Free & Halogen-Free) | [DATA_NEEDED: RoHS status] |
| Speed Grade | -RDC (see datasheet for bin timing) | — |
| Family | H5AN8G4NAFR-xxC / H5AN8G8NAFR-xxC / H5AN8G6NAFR-xxC | — |
| Max Clock Rate | [DATA_NEEDED: max clock rate for -RDC bin] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +85C |
| 資料速率 | — | 2400 MT/s |
| Clock Architecture | — | Differential clock (CK_t / CK_c), fully synchronous |
| 封裝 | — | 96-ball FBGA (TFBGA) |
| Refresh | — | Auto self-refresh |
| Precharge | — | Auto precharge function |
| Reset | — | Asynchronous reset function |
| Data Mask | — | DM function supported |
| Termination | — | Dynamic on-chip termination (ODT) |
| Calibration | — | ZQ calibration function |
| Error Checking | — | CRC function |
| Write Leveling | — | Write leveling function supported |