SN65MLVD200ADR vs DS90C402M 比較
詳細並排比較 SN65MLVD200ADR 由 Texas Instruments 與 DS90C402M 由 Texas Instruments. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | SN65MLVD200ADR | DS90C402M |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 類別 | Interface ICs | Interface ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 功能 | Half-duplex M-LVDS transceiver (1 driver + 1 receiver) | — |
| 資料速率 | Up to 100 Mbps (typical) | — |
| Driver Skew | 700 ps (typical) | — |
| 供應電壓 | 3.3 V (typical) | — |
| Output Drive Current | 24 mA (typical) | — |
| ESD Protection (Bus Pins) | ±9 kV HBM | — |
| Common-Mode Range (Receiver) | -1 V to +3.4 V (M-LVDS spec) | — |
| Standards Compliance | TIA/EIA-899 (M-LVDS); TIA/EIA-644 (LVDS reference) | — |
| 工作溫度 | -40 °C to +85 °C | — |
| 封裝 | 8-pin SOIC | 8-lead SOIC |
| 安裝類型 | Surface Mount | Surface mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| 腳位數 | 8 | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Device Type | — | Dual LVDS receiver |
| Receiver Configuration | — | 2 receivers |
| Input Threshold Sensitivity | — | ±100 mV |
| Common-Mode Noise Protection | — | Supported |
| Data-Rate Optimization | — | High data rate |
| Power Optimization | — | Low power |
| Interface Pairing | — | DS90C401 companion device |
| 拓撲 | — | Dual high-speed point-to-point interface |
| Package Family | — | SOIC surface-mount package family |
| 腳位數 | — | 8 |
| 工作電源電壓 | — | [DATA_NEEDED: operating supply voltage] |
| Propagation Delay | — | [DATA_NEEDED: propagation delay] |
| Input Common-Mode Range | — | [DATA_NEEDED: input common-mode voltage range] |
| Maximum Data Rate | — | [DATA_NEEDED: maximum data rate] |
| 供應電流 | — | [DATA_NEEDED: supply current] |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Differential Input Termination | — | [DATA_NEEDED: input termination requirement] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |
| MSL | — | [DATA_NEEDED: moisture sensitivity level] |