ATSAMA5D28C-LD1G-CUR - Cortex-A5 MPU 500MHz 289-LFBGA | Microchip
MPN： ATSAMA5D28C-LD1G-CUR ✓ 啟用中ATSAMA5D28C-LD1G-CUR 概覽
An Arm Cortex-A5 MPU is a 32-bit application-class processor core based on the ARMv7-A architecture, designed for low-power Linux and RTOS workloads in cost-sensitive embedded products. The Cortex-A5 family sits between the microcontroller-class Cortex-M cores and the higher-performance Cortex-A7/A9 cores, offering full application processor capability (MMU, caches, NEON/FPU optional) at relatively low power. The ATSAMA5D28C-LD1G-CUR belongs to Microchip's SAMA5D2 family, a line of heterogeneous MPUs that pair an Arm Cortex-A5 host core with the Cortex-M4 for real-time system control, and that target HMI, connectivity gateway, and industrial control applications.
Key differentiating features include 32 Kbytes of I-cache and 32 Kbytes of D-cache with NEON and FPU extensions, a 16-bit DDR2/LPDDR2/LPDDR3 external memory controller in addition to the integrated SiP memory, and a rich set of peripherals: two HS USB ports with PHY, two CAN-FD controllers, three FLEXCOMs (USART/SPI/TWI), a 1 Gbit Ethernet GMAC with 1588 support, an LCD controller up to WXGA, and an image sensor interface. Advanced security is provided by secure boot, hardware crypto accelerators (AES, SHA, TRNG), and tamper detection pins, making the part suitable for hardened edge devices.
The SAMA5D28 architecture uses a 65 nm low-power CMOS process and supports Linux (mainline), FreeRTOS via the M4 companion, and bare-metal SDK environments. The integrated SiP memory reduces BOM cost and eliminates the DDR PCB routing complexity that normally consumes four to six PCB layers, which is the central value proposition for compact, high-density designs.
Typical applications include industrial HMI panels, IoT edge gateways, building automation controllers, smart appliances, POS terminals, medical patient-monitoring displays, and 4G/LTE router CPE. For each of these the SiP integration, low-power profile, and Linux mainline support significantly shorten time-to-market. The part is also well-suited as an upgrade for legacy Cortex-A5 designs that need additional working memory.
When designing with this MPU, allocate PCB space for the 289-ball LFBGA escape routing (0.8 mm ball pitch) and ensure the four-layer minimum stack-up uses impedance-controlled traces for the DDR2/LPDDR2 paths. Plan boot media (QSPI NOR or e.MMC) carefully and use Microchip's SAMA5D2 System-in-Package BSP for Linux to reduce software bring-up time. For harsh environments, leverage the industrial -40C to +85C temperature range and on-die tamper features.
This page synthesizes distributor pricing, drop-in alternative comparisons, and practical PCB/software design notes not consolidated on the manufacturer datasheet.
直接替換替代品，適用於 ATSAMA5D28C-LD1G-CUR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ATSAMA5D28C-LD1G-CUR （相同外形與佔位） — 差異在於 Package, USB, Ethernet, Operating Temperature, Core Architecture.
ATSAMA5D28C-LD2G-CUR
✅ 直接替換聯絡詢價
查看資料表 →ATSAMA5D28C-D1G-CU
✅ 直接替換聯絡詢價
查看資料表 →ATSAMA5D28C-LD1G-CU
✅ 直接替換聯絡詢價
查看資料表 →ATSAMA5D27C-LD1G-CU
✅ 直接替換聯絡詢價
查看資料表 →ATSAMA5D28B-CUR
✅ 直接替換聯絡詢價
查看資料表 →ATSAMA5D28C-LD1G-CUR 最大額定值與電氣特性
| MPU Core | ARM Cortex-A5 |
| Core Count | 1 |
| 資料匯流排寬度 | 32-bit |
| Maximum CPU Clock | 500 MHz |
| Integrated Memory (SiP) | 2 Gbit LPDDR2 SDRAM |
| External Memory Support | DDR2, LPDDR2, LPDDR3, QSPI, e.MMC |
| L1 I-Cache / D-Cache | 32 Kbytes / 32 Kbytes |
| NEON / FPU | Yes (with single-precision FPU) |
| Operating Voltage (Core) | 1.2 V |
| Package Type | 289-LFBGA |
| Package Dimensions | 14 x 14 mm |
| Ball Pitch | 0.8 mm |
| 工作溫度 | -40C to +85C (Industrial) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
ATSAMA5D28C-LD1G-CUR 14 x 14 mm 腳位配置指南
ATSAMA5D28C-LD1G-CUR（14 x 14 mm 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： ATSAMA5D28C-LD1G-CUR.
請參閱 資料表 以查看完整腳位配置。
典型應用
ATSAMA5D28C-LD1G-CUR 適用於 6 應用s: Industrial HMI Panels, IoT Edge Gateways, Building Automation Controllers, Smart Appliances / White Goods, POS Terminals, Medical Patient-Monitoring Displays.
Industrial HMI Panels
The ATSAMA5D28C-LD1G-CUR's 500 MHz Cortex-A5 core plus 2 Gbit integrated LPDDR2 provides ample headroom for Linux-driven Qt/GTK graphical HMIs at WXGA resolution. Its dedicated LCD controller (RGB up to WXGA at 60 fps) and on-chip touch controller I2C interface eliminate the need for an external graphics chip. Industrial -40C to +85C rating suits factory-floor deployments, while secure boot protects factory configuration IP.
推薦
IoT Edge Gateways
The ATSAMA5D28C-LD1G-CUR's dual GMAC with IEEE 1588, dual CAN-FD, two HS USB ports, and three FLEXCOMs make it a multi-protocol gateway in a single chip. The 2 Gbit LPDDR2 SiP handles TLS/IPsec encrypted traffic buffers, while the Cortex-M4 companion core manages real-time sensor sampling. The SiP form factor reduces the gateway BOM and allows a 4-layer PCB instead of the 6+ layers an external DDR design would need.
推薦
Building Automation Controllers
Building automation controllers benefit from the ATSAMA5D28C-LD1G-CUR's RS-485-capable FLEXCOMs (for Modbus and BACnet), Ethernet with PTP (for HVAC synchronization), and Cortex-M4 for real-time lighting loop control. The integrated 2 Gbit LPDDR2 supports BACnet trend-log buffers and KNX/IP stack tables. Linux mainline support means BACnet stacks (libiec61850, openbld) build without vendor patches.
推薦
Smart Appliances / White Goods
Smart appliances such as connected ovens, washing machines, and HVAC indoor units use the ATSAMA5D28C-LD1G-CUR to drive a color LCD, run a connected mobile app, and manage multiple motor/sensor feedback loops. The Cortex-A5 runs a Linux Yocto distribution with Qt for UI, while the Cortex-M4 handles hard real-time motor control PWM, making it a heterogeneous processing platform. Its low-power modes suit Energy Star standby budgets.
推薦
POS Terminals
POS terminals rely on the ATSAMA5D28C-LD1G-CUR's 2 Gbit LPDDR2 SiP to buffer payment cryptographic operations (RSA, ECC, AES) without external DRAM, while the secure-boot and tamper-detect pins protect PIN-pad keys. The display controller drives the cashier LCD and the customer-facing second display, while the image sensor interface supports an optional 1D/2D barcode camera. EMVCo and PCI-PTS 6 compliance are achievable with proper firmware.
推薦
Medical Patient-Monitoring Displays
The ATSAMA5D28C-LD1G-CUR's industrial temperature range and IEC 60601-1 ready design (when paired with proper isolation) make it suitable for bedside patient monitors. Its WXGA LCD controller drives a 7-10 inch clinical display, the Cortex-A5 runs the HL7/FHIR stack, and the on-chip crypto accelerators handle DICOM encryption. The 2 Gbit LPDDR2 SiP provides the memory bandwidth needed for multi-parameter waveform rendering.
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推薦產品摘要
工程參考資料，適用於 ATSAMA5D28C-LD1G-CUR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ATSAMA5D28C-LD2G-CUR | ATSAMA5D28C-D1G-CU | ATSAMA5D28C-LD1G-CU | ATSAMA5D27C-LD1G-CU | ATSAMA5D28B-CUR |
|---|---|---|---|---|---|---|
| Package | 289-LFBGA (14x14) | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same |
| Brand | Microchip Technology | Microchip Technology - same | Microchip Technology - same | Microchip Technology - same | Microchip Technology - same | Microchip Technology - same |
| Core / Clock | Cortex-A5 / 500 MHz | Cortex-A5 / 500 MHz - same | Cortex-A5 / 500 MHz - same | Cortex-A5 / 500 MHz - same | Cortex-A5 / 500 MHz - same | Cortex-A5 / 500 MHz - same |
| Integrated SiP Memory | 2 Gbit LPDDR2 | 4 Gbit LPDDR2 (+100%) | 1 Gbit DDR2 (different type, -50%) | 1 Gbit LPDDR2 (-50%) | 1 Gbit LPDDR2 (-50%) | No SiP memory, external DDR required |
| Ethernet GMAC | 2 (with IEEE 1588) | 2 - same | 2 - same | 2 - same | 1 (D27 family has 1 GMAC) | 2 - same (B-revision) |
| CAN-FD Controllers | 2 | 2 - same | 2 - same | 2 - same | 1 (D27 family reduced) | 2 - same (B-revision) |
| Tamper Detection / Secure Boot | Yes (C-revision hardened) | Yes - same | Yes - same | Yes - same | Yes (C-revision) | Basic secure boot only, no tamper pins |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same |
主要差異化特點
- 2 Gbit integrated LPDDR2 SiP eliminates external DDR routing (對比ATSAMA5D28B-CUR)
- C-revision enhanced security with tamper detection pins (對比ATSAMA5D28B-CUR)
- Dual Ethernet GMAC vs single GMAC in D27 family (對比ATSAMA5D27C-LD1G-CU)
- Larger integrated LPDDR2 than the LD1G-CU sibling (對比ATSAMA5D28C-LD1G-CU)
設計說明
The 289-LFBGA with 0.8 mm ball pitch requires a 4-layer PCB stack-up minimum, with the top layer dedicated to BGA escape, internal layers for high-speed signal routing, and a continuous ground plane on layer 4. Use Microchip's SAMA5D2 SiP reference design (Gerber set) as a starting point. Microvia (HDI) fabrication is recommended; standard 0.2 mm laser-drilled microvias avoid the dog-bone fanout complexity that through-hole vias would create. Match trace lengths for DDR2/LPDDR2 data lanes to within 25 mil of each other and the clock within 50 mil of the strobe to maintain signal integrity at 500 MHz operation.
The ATSAMA5D28C-LD1G-CUR typical power consumption is 1.5 W at full Cortex-A5 load with peripherals active. Estimated: with theta_JA of approximately 25 C/W on a standard 4-layer JEDEC test board, the junction-to-ambient temperature rise is ~38 C at peak load. In an enclosed industrial enclosure at 60 C ambient, the junction reaches ~98 C, which is still below the 100 C typical Tj_max but leaves little margin. For sealed enclosures add a small copper heat-spreader or thermal via array under the BGA to reduce theta_JA by 30-40%. The LFBGA's bottom-side thermal pad should be soldered to the PCB thermal land for best heat extraction.
Three common pitfalls when bringing up the ATSAMA5D28C-LD1G-CUR: (1) the boot mode straps (BMS) must be pulled correctly at reset - a floating strap on BMS[1:0] can leave the MPU in serial boot mode and confuse the host programmer; (2) the SiP LPDDR2 requires careful ZQ calibration and the DDR PHY register sequence must come from the latest SAMA5D2 BSP - older bootloaders sometimes initialize the SiP as standard DDR2, causing intermittent crashes; (3) the LCD controller's pixel clock must be sourced from a programmed PLL, not the main oscillator, to avoid jitter visible as pixel noise on WXGA panels. Always validate boot with the Microchip SAM-BA utility before flashing application images.
合規資訊
RoHS and REACH compliance per Microchip product page. Not AEC-Q100 qualified - automotive designs should use the ATSAMA5D2x-CUR automotive-graded variants instead. Industrial -40C to +85C operating temperature supports most industrial environments.
