IQEH84NE2LM7UCGATMA1 - 25V OptiMOS 7 N-FET, 275A | Infineon
MPN： IQEH84NE2LM7UCGATMA1 ✓ 啟用中IQEH84NE2LM7UCGATMA1 概覽
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled semiconductor switch used for power conversion, motor drive, and load switching. It belongs to the hierarchy: discrete semiconductor → transistor → FET → power MOSFET. The 25 V OptiMOS 7 family sits at the low-voltage end of Infineon's power MOSFET portfolio, optimised for synchronous rectification, OR-ing, hot-swap, and battery-protection switching in telecom, server, and e-mobility auxiliary systems.
Key differentiators include an ultra-low RDS(on) of 1.0 mΩ typical at VGS=10 V, gate-charge optimisation for fast turn-on/off transitions, a 175 °C operating junction temperature rating, and an exposed-die/source-down PG-TTFN-9-3 package engineered for minimal thermal resistance from junction to PCB. The OptiMOS 7 cell architecture trims both switching and conduction losses versus OptiMOS 5/6 predecessors, allowing higher current density per footprint.
The PG-TTFN-9-3 package provides a top-side-cooled source-down land pattern that pulls heat directly into the PCB copper, eliminating top-side heatsinking. The 175 °C Tj-max rating supports operation in confined, high-ambient environments such as server SMPS secondary-side synchronous rectification stages and 12 V/24 V hot-swap controllers. The VGS(th) is characterised in the low-voltage logic-level range, simplifying gate drive from 5 V-class MCUs or PWM controllers.
Typical applications include synchronous rectification in 12 V-25 V DC-DC buck converters, hot-swap / eFuse protection in server 12 V rails, battery protection and load switching in 24 V battery packs, OR-ing FETs in redundant telecom supplies, and motor drive half-bridges in low-voltage BLDC fans and pumps. For all applications, the source-down PG-TTFN-9-3 footprint lets PCB copper serve as the heatsink.
When designing with this part, observe the SOA curve carefully: although it can pulse 275 A, sustained DC current at Ta is limited by 2.5 W dissipation. Maximise copper area on source pads to keep Tj below 125 °C; derate above 80 °C ambient for reliability. Pair it with a gate-driver capable of >2 A peak source/sink current to exploit OptiMOS 7's low Qg and fast switching edges.
This page synthesises Infineon OptiMOS 7 family datasheet parameters, Infineon part-page electrical ratings, distributor pricing as of 2026-09-15, and a drop-in alternative list drawn from same-family Infineon parts, not found on the bare distributor listings.
直接替換替代品，適用於 IQEH84NE2LM7UCGATMA1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： IQEH84NE2LM7UCGATMA1 （相同外形與佔位） — 差異在於 Package, Technology, Operating Temperature Range, RoHS Status, Continuous Drain Current (ID) at Ta.
IQEH68NE2LM7UCGATMA1
✅ 直接替換聯絡詢價
查看資料表 →IQEH54NE2LM7UCGATMA1
✅ 直接替換聯絡詢價
查看資料表 →IQEH50NE2LM7UCGATMA1
✅ 直接替換📋 參考替代品（不在目錄中）
IQEH50NE2LM7UCGSCATMA1
✅ 直接替換聯絡詢價
查看資料表 →IQDH88N06LM5CGSCATMA1
✅ 直接替換聯絡詢價
查看資料表 →IQDH29NE2LM5CGSCATMA1
✅ 直接替換聯絡詢價
查看資料表 →IQEH84NE2LM7UCGATMA1 最大額定值與電氣特性
| FET Type | N-Channel |
| Technology | OptiMOS 7 (Trench MOSFET) |
| Drain-Source Voltage (VDS) | 25 V |
| Continuous Drain Current (ID) at Ta | 42 A |
| Pulsed Drain Current (IDM) at Tc | 275 A |
| Power Dissipation (PD) at Ta | 2.5 W |
| Power Dissipation (PD) at Tc | 107 W |
| 工作接面溫度 | -55 C to +175 C |
| 封裝 | PG-TTFN-9-3 (surface mount, source-down) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Lead-Free | Yes |
| Switching Application | Hard- and soft-switching |
IQEH84NE2LM7UCGATMA1 pg-ttfn-9-3 (surface mount, source-down) 腳位配置指南
IQEH84NE2LM7UCGATMA1（pg-ttfn-9-3 (surface mount, source-down) 封裝）的腳位配置。 此功率元件具有閘極、汲極與源極端子。對於非極性封裝，請參閱製造商資料表以取得確切的第 1 腳方向與佈局詳細資訊。常見應用包括電源設計、馬達驅動與負載切換。
無詳細腳位定義資料： IQEH84NE2LM7UCGATMA1.
請參閱 資料表 以查看完整腳位配置。
典型應用
IQEH84NE2LM7UCGATMA1 適用於 7 應用s: 12 V-24 V Synchronous Rectification in DC-DC Buck Converters, Hot-Swap / eFuse Protection in 12 V Server Rails, Battery Protection and Load Switching in 24 V Battery Packs, OR-ing FETs in Redundant Telecom Supplies, Motor-Drive Half-Bridges in 24 V BLDC Fans and Pumps, USB Power Delivery (PD) Load Switch, Solar Micro-Inverter Low-Side Switch.
12 V-24 V Synchronous Rectification in DC-DC Buck Converters
The IQEH84NE2LM7UCGATMA1 fits synchronous rectification in 12 V-24 V buck converters where its 25 V VDS rating covers the rail with margin and the OptiMOS 7 cell minimises body-diode reverse-recovery loss. With RDS(on) in the low single-digit mΩ range at VGS=10 V and a low Qg, conduction loss at 30 A-40 A load is far below what a Schottky rectifier could achieve, raising efficiency by 2-4 percentage points. The source-down PG-TTFN-9-3 package pulls heat into the PCB copper, eliminating top-side heatsinking. Drive it from a 5 V-10 V gate-driver with >2 A peak current to fully exploit OptiMOS 7 switching edges.
推薦
Hot-Swap / eFuse Protection in 12 V Server Rails
The IQEH84NE2LM7UCGATMA1 is well-suited for hot-swap and eFuse protection on 12 V server backplanes. Its 275 A pulsed drain current rating handles inrush transients, while the 25 V VDS withstands voltage transients on 12 V rails. The device's low RDS(on) keeps steady-state conduction loss low at 20 A-30 A server load currents, and the PG-TTFN-9-3 source-down package dissipates heat directly into the PCB. Pair it with a hot-swap controller that monitors VDS for current-limit foldback; OptiMOS 7's linear-mode SOA supports brief overloads during connector mating events.
推薦
Battery Protection and Load Switching in 24 V Battery Packs
In 24 V battery packs the IQEH84NE2LM7UCGATMA1 acts as the protection / load-switch FET. The 25 V VDS comfortably covers a fully-charged 24 V stack with transients, and the 275 A pulsed rating handles motor inrush when the pack drives a 24 V BLDC fan. OptiMOS 7's low RDS(on) at VGS=4.5 V allows direct drive from a low-voltage BMS microcontroller, simplifying BOM and shrinking the PCB. Use two IQEH84NE2LM7UCGATMA1 in back-to-back source configuration for true bidirectional disconnect if needed.
推薦
OR-ing FETs in Redundant Telecom Supplies
For redundant -48 V telecom rails stepped down to 12 V-24 V distribution, the IQEH84NE2LM7UCGATMA1 works as an OR-ing FET between parallel PSU outputs. Its 25 V VDS handles the secondary-side rail, and the low RDS(on) keeps the diode-OR voltage drop low, eliminating the need for a Schottky barrier. The source-down PG-TTFN-9-3 package fits standard PSU daughter-card footprints. Drive the gate from an OR-ing controller that pulls VGS below threshold during reverse-current detection for fast turn-off.
推薦
Motor-Drive Half-Bridges in 24 V BLDC Fans and Pumps
The IQEH84NE2LM7UCGATMA1 works in the low-side (or high-side, depending on topology) of a 24 V BLDC fan or pump half-bridge. Its 25 V rating handles 24 V bus transients and back-EMF, while the 275 A pulsed rating covers motor-startup inrush. OptiMOS 7's low Qgd enables PWM frequencies above 25 kHz, which keeps motor current ripple below audible thresholds. The PG-TTFN-9-3 package dissipates switching losses into PCB copper without an external heatsink.
推薦
USB Power Delivery (PD) Load Switch
In USB PD sink applications the IQEH84NE2LM7UCGATMA1 acts as the VBUS load switch between the Type-C connector and the downstream regulator. Its 25 V VDS handles 20 V PD contracts with margin, and the 42 A continuous rating easily passes 100 W (5 A) PD profiles. The PG-TTFN-9-3 package keeps the load switch small enough to fit inside a Type-C dongle enclosure. Drive the gate from a low-side load-switch controller that supports fast turn-off for over-current protection.
推薦
Solar Micro-Inverter Low-Side Switch
In a low-voltage solar micro-inverter the IQEH84NE2LM7UCGATMA1 can act as the low-side synchronous switch in a 25 V-class full-bridge driven from a single 12 V-24 V PV panel. The 25 V VDS handles the rail with margin and the low RDS(on) reduces conduction loss under continuous solar-harvesting load. The PG-TTFN-9-3 source-down footprint pulls heat directly into the aluminium PCB back-plate typical of outdoor solar enclosures. Use a 180°-out-of-phase gate drive to balance thermal stress between high- and low-side FETs.
推薦
推薦產品摘要
工程參考資料，適用於 IQEH84NE2LM7UCGATMA1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | IQEH68NE2LM7UCGATMA1 | IQEH54NE2LM7UCGATMA1 | IQEH50NE2LM7UCGATMA1 | IQDH88N06LM5CGSCATMA1 |
|---|---|---|---|---|---|
| Package | PG-TTFN-9-3 (source-down) | PG-TTFN-9-3 - same | PG-TTFN-9-3 - same | PG-TTFN-9-3 - same | PG-TTFN-9-3 - same |
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon |
| Technology | OptiMOS 7 | OptiMOS 7 | OptiMOS 7 | OptiMOS 7 | OptiMOS 5 LM |
| Drain-Source Voltage (VDS) | 25 V | 25 V | 25 V | 25 V | 60 V |
| RDS(on) Grade (family code) | 84 (lowest in family) | 68 | 54 | 50 | 88 |
| Maximum Junction Temperature | 175 C | 175 C (OptiMOS 7 family) | 175 C (OptiMOS 7 family) | 175 C (OptiMOS 7 family) | 175 C (OptiMOS 5 family) |
| Mounting Type | Surface Mount (source-down) | Surface Mount (source-down) | Surface Mount (source-down) | Surface Mount (source-down) | Surface Mount (source-down) |
主要差異化特點
- Lowest RDS(on) grade ('84') in 25 V OptiMOS 7 family (對比IQEH68NE2LM7UCGATMA1)
- OptiMOS 7 cell technology (對比IQDH88N06LM5CGSCATMA1)
- Source-down PG-TTFN-9-3 package (對比IRF7854TRPBF (PQFN/DFN-style FET))
設計說明
Estimated: at VIN=12 V, VOUT=1 V, IOUT=40 A continuous, power dissipation in the FET is roughly (12-1) * 40 * (1-D) where D=VOUT/VIN is the duty cycle. For a synchronous-rectifier low-side FET with VIN=12 V / VOUT=5 V, conduction loss is I²RDS(on); with RDS(on) of 1.0 mΩ, loss is 40² * 0.001 = 1.6 W. The PG-TTFN-9-3 source-down package needs a copper pour of at least 1 square inch to keep Tj below 125 °C at full load. Above 80 °C ambient, derate current by ~50 mA per °C.
Use a Kelvin-source connection (separate gate-driver return pin tied to the source pad near the die) to avoid source-inductance oscillations that can re-trigger the FET. Place input ceramic bypass capacitors (10 µF X7R + 0.1 µF NP0) within 5 mm of the drain and source pads to suppress VDS ringing. The source-down PG-TTFN-9-3 outline routes all heat into the PCB, so stitch thermal vias under the source pad to the opposite inner copper plane.
Do not exceed VGS=±20 V (absolute max) — most gate drivers run at 10 V, which is safe, but during transient ringing a poorly designed boot-strap supply can overshoot. Confirm VDS transients (from leakage inductance) stay below 25 V with at least 20% margin; add an RCD snubber if measured transients exceed 20 V. Always sequence gate turn-off before disconnecting drain current in hot-swap applications to avoid uncontrolled avalanche.
Estimated: OptiMOS 7 reduces both Qg and Qgd relative to OptiMOS 5/6. For a 12 V buck converter switching at 500 kHz with 40 A load, gate-drive loss per FET is Qg * VGS * fsw ≈ 30 nC * 10 V * 500 kHz = 150 mW. Use a gate-driver with >2 A peak source/sink current (e.g. 2EDL6014ACG2DXTMA1 family) to fully exploit the fast turn-on/off transitions without ringing.
合規資訊
RoHS compliant per Infineon product page; AEC-Q100 not applicable (this is a discrete power MOSFET, not an automotive-qualified IC).
