10AS057K2F35I1HG - Arria 10 SX SoC FPGA, 570K LE, 1152-FCBGA | Intel
料号： 10AS057K2F35I1HG ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $4682.11 | $4,682.11 |
| 10 | $4450 | $44,500.00 |
| 50 | $4220 | $211,000.00 |
| 100 | $4015 | $401,500.00 |
| 250 | $3820 | $955,000.00 |
10AS057K2F35I1HG 概述
An SoC FPGA integrates a general-purpose processor subsystem and programmable logic on a single die, enabling deterministic real-time control alongside software flexibility. In the Altera/Intel Arria 10 SX hierarchy, the 570K LE device sits in the mid-density range above the 10AS048 and below the 10AS066/10AS660 density grades, and the 'K2' speed grade positions it between the slower K1 and faster K3/H transceivers. Compared with discrete CPU+FPGA designs, an SoC FPGA reduces board area, BOM, and inter-chip latency by collapsing two devices into one.
Key features include 570K logic elements, ARM Cortex-A9 dual-core hard processor with CoreSight debug, 396 user I/O, integrated transceivers supporting multi-gigabit serial links, embedded DSP blocks, and on-chip M20K memory blocks. The device is offered in industrial temperature grade (I1 = -40C to +100C), and the FCBGA 35x35 mm package uses 1 mm ball pitch with flip-chip attach for high signal integrity and thermal performance.
The Arria 10 SX architecture uses a 20 nm process with Adaptive Logic Module (ALM) fabric, variable-precision DSP blocks, and hardened memory controllers, DDR4 PHY, and PCI Express Gen3 IP. The integrated ARM subsystem runs a separate power island, allowing the FPGA fabric to operate while the HPS is held in reset for low-power sequencing or asymmetric power-gating.
Typical applications include wireless baseband processing, radar and electronic warfare signal chains, industrial machine vision, broadcast video processing, and high-performance embedded compute. The SoC integration makes it especially attractive when deterministic hardware acceleration must coexist with an operating system for control-plane tasks.
Designers should plan the HPS boot flash, the HPS-to-FPGA bridge clocking, and the DDR4 pin assignment early; mis-assigned HPS EMIF pins cannot be migrated to general-purpose I/O. Power estimation must include both the FPGA fabric and the ARM subsystem, since the HPS contributes a fixed ~5-10 W floor regardless of fabric utilization.
This page combines distributor pricing, drop-in same-package alternatives, and design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and qualifying the 10AS057K2F35I1HG in production designs.
直接替换替代料： 10AS057K2F35I1HG ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： 10AS057K2F35I1HG （相同外形与封装尺寸） ——差异在于 Speed Grade, Package, RoHS Status, Mounting Type, Process Node.
快速对比工具——选择替代料号进行并排对比：
10AS057K2F35E1HG
✅ 直接替换✓ 有现货
$1995 / 个
查看数据手册 →10AS057K2F35E2SG
✅ 直接替换✓ 有现货
$2304.55 / 个
查看数据手册 →10AS057K2F35E2LG
✅ 直接替换✓ 有现货
$3450 / 个
查看数据手册 →10AS066K2F35I1HG
✅ 直接替换📋 参考替代料（不在目录中）
10AS057K1F35I1HG
✅ 直接替换✓ 有现货
$5210 / 个
查看数据手册 →10AS057K2F35I1HG 最大额定值与电气特性
| Device Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570K |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Fabric Frequency | 1.5 GHz |
| User I/O Count | 396 |
| 封装 | 1152-FBGA, FC (35x35 mm) |
| Speed Grade | K2 (mid) |
| Temperature Grade | Industrial (I1: -40C to +100C) |
| 安装类型 | Surface Mount (Flip-Chip BGA) |
| Process Node | 20 nm |
| Embedded Memory | M20K blocks |
| Hard Memory Controllers | DDR4 with hard PHY |
| PCIe Hard IP | PCI Express Gen3 |
| RoHS 状态 | Compliant |
| Lead-Free | Yes |
10AS057K2F35I1HG 1152-fbga, fc (35x35 mm) 引脚配置指南
10AS057K2F35I1HG（1152-fbga, fc (35x35 mm) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： 10AS057K2F35I1HG.
请参阅 数据手册 以查看完整引脚配置。
典型应用
10AS057K2F35I1HG 适用于 6 应用s: Wireless Baseband Processing, Radar and Electronic Warfare Signal Chains, Industrial Machine Vision, Broadcast Video Processing, High-Performance Embedded Compute, Medical Imaging Equipment.
Wireless Baseband Processing
The 10AS057K2F35I1HG's 570K logic elements and embedded variable-precision DSP blocks deliver the throughput needed for multi-antenna wireless baseband signal chains, including LTE/5G NR channel decoding, crest-factor reduction (CFR), and digital predistortion (DPD). The dual-core ARM Cortex-A9 MPCore runs the Layer-2/3 stack, MAC scheduler, and Ethernet backhaul, while the FPGA fabric handles the deterministic, sample-rate DSP. With 396 user I/O plus integrated multi-gigabit transceivers and hard PCI Express Gen3, the device interfaces to RFICs, ADCs/DACs, and host processors without external glue logic. Power estimation: 20-35 W typical at full LTE 4x4 MIMO utilization. This makes it an ideal SoC FPGA for small-cell and macro base station designs.
推荐
Radar and Electronic Warfare Signal Chains
The 10AS057K2F35I1HG suits phased-array radar and EW receivers that demand deterministic latency and high compute density. The 570K LE fabric plus hardened DSP blocks execute FFTs, pulse compression, and beamforming at sample rates beyond CPU capability, while the ARM Cortex-A9 HPS hosts the control plane, threat library, and Ethernet/serial recorder interfaces. Hardened DDR4 with PHY simplifies the high-bandwidth capture/playback buffer, and PCI Express Gen3 supports direct attach to FPGAs or CPUs for back-end processing. Industrial (I1) -40C to +100C temperature operation covers outdoor and shipborne enclosures. Estimated throughput: tens of GFLOPS sustained DSP, multiple GSPS ADC interface via LVDS/SerDes.
推荐
Industrial Machine Vision
The 10AS057K2F35I1HG accelerates high-speed line-scan and area-scan machine vision pipelines, executing pre-processing (flat-field correction, Bayer demosaic, color conversion), feature extraction, and AI inference offload in the FPGA fabric. The dual-core ARM Cortex-A9 HPS runs the vision OS, GigE Vision / CoaXPress / Camera Link stacks, and PROFINET/EtherCAT industrial networking. Industrial (I1) temperature grade and 396 user I/O support factory-floor deployment with multiple cameras and discrete I/O. Power: 15-25 W typical for 4-camera systems. Compared with a CPU-only vision system, this SoC FPGA delivers 5-10x throughput per watt at deterministic frame rates.
推荐
Broadcast Video Processing
The 10AS057K2F35I1HG handles 4K/UHD broadcast video processing, including real-time HEVC/H.264 encode/decode assist, color space conversion, deinterlacing, scaling, and overlay composition in the 570K LE fabric. The ARM Cortex-A9 HPS runs the broadcaster control plane, transport stream muxing, and IP network interfaces. The 396 user I/O plus high-speed transceivers handle SDI (SMPTE 2022, 424, 2082) interfaces via external PHY or transceiver tiles, and hard PCI Express Gen3 supports ingest from SSD arrays or accelerator cards. Industrial temperature grade supports studio and outside-broadcast use.
推荐
High-Performance Embedded Compute
The 10AS057K2F35I1HG combines deterministic FPGA acceleration with a Cortex-A9 Linux-capable subsystem, making it ideal for industrial embedded compute nodes that must process high-rate sensor data while also running networking and control-plane software. The hard ARM subsystem runs Yocto or Buildroot Linux with industrial protocols (OPC-UA, MQTT, Modbus/TCP), while the 570K LE fabric accelerates custom DSP, control loops, and cryptography. The 1152-FCBGA 35x35 mm package is a compact form factor for DIN-rail or panel-mount embedded systems. Estimated power budget: 18-30 W at moderate fabric utilization.
推荐
Medical Imaging Equipment
The 10AS057K2F35I1HG serves as the central compute and accelerator in ultrasound, endoscopy, and CT/MRI front-end systems. The FPGA fabric performs beamforming, FIR filtering, image reconstruction, and real-time display processing, while the ARM Cortex-A9 HPS runs the user interface, network stack, and DICOM storage. The industrial temperature range and high pin count accommodate multi-channel analog front ends and display interfaces. Hardened DDR4 and PCI Express Gen3 simplify high-bandwidth data movement, reducing BOM cost versus a CPU+discrete-FPGA architecture.
推荐
推荐产品汇总
工程参考数据： 10AS057K2F35I1HG ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 10AS057K2F35E1HG | 10AS057K2F35E2SG | 10AS057K2F35E2LG | 10AS066K2F35I1HG | 10AS057K1F35I1HG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA, FC (35x35 mm) | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same |
| Logic Elements | 570K | 570K | 570K | 570K | 660K | 570K |
| Speed Grade | K2 (mid) | K2 (mid) | K2 (mid) | K2 (mid) | K2 (mid) | K1 (slower) |
| Temperature Grade | I1 (industrial, -40C to +100C) | E1 (commercial, 0C to +100C) | E2 (commercial) | E2 (commercial) | I1 (industrial) | I1 (industrial) |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight |
| Approx. Unit Price (qty 1) | $4,682.11 | Similar (commercial temp, lower) | Similar | Similar | Higher (density upgrade ~10-20%) | Similar |
关键差异点
- Industrial temperature grade in the same F35 footprint （对比 10AS057K2F35E1HG)
- 570K LE in the mid-density F35 package （对比 10AS066K2F35I1HG)
- K2 mid speed grade is faster than K1 at same density （对比 10AS057K1F35I1HG)
设计说明
Estimated: the Arria 10 SX 570K device can dissipate 20-40 W under typical wireless baseband or radar workloads. The 1152-FCBGA 35x35 mm package must be paired with a thermal interface material (TIM) and finned heatsink plus forced-air flow of at least 200 LFM. Use the Intel Arria 10 PowerPlay early power estimator before PCB layout to size cooling and verify junction temperature stays below 100C for industrial (I1) grade. Never rely on the package alone to dissipate power at high toggle rates.
Plan the HPS boot flash, the HPS-to-FPGA bridge clocking, and the HPS EMIF (DDR4) pin assignment in the early schematic stage; mis-assigned HPS EMIF pins cannot be migrated to general-purpose I/O. Use the Intel Arria 10 SoC FPGA pin connection guidelines to route JTAG, configuration, and reference clocks separately from high-speed transceiver channels. Provide a minimum of 4 PCB layers with continuous ground planes under the BGA for transceiver return-path integrity.
Do not assume the HPS can boot from any flash device - the Arria 10 SX HPS only supports specific QSPI/NAND/NOR boot modes and pin assignments per the SoC boot guide. Also, the ARM subsystem contributes a fixed ~5-10 W power floor regardless of fabric utilization, so total-board thermal budgets must include this. Finally, configuration via JTAG requires the 10-pin or 20-pin Altera/Intel header, while passive serial configuration requires an external EPCQ or compatible flash.
合规信息
RoHS and REACH compliance per Intel/Altera product page. AEC-Q100 not applicable (FPGA SoC is not an automotive-qualified IC at this density; automotive variants would carry a different ordering code).
