10AS057K1F35I1HG - Arria 10 SX SoC FPGA, 570K LE, 1152-FBGA | Intel
MPN: 10AS057K1F35I1HG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5636.75 | $5,636.75 |
| 5 | $5560.12 | $27,800.60 |
| 10 | $5480.5 | $54,805.00 |
| 25 | $5380 | $134,500.00 |
| 100 | $5210 | $521,000.00 |
Drop-in alternatives for 10AS057K1F35I1HG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AS057K1F35I1SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AS057K2F35I1HG
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$3820 / Unit
View Datasheet β10AS057K2F35E1HG
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1995 / Unit
View Datasheet β10AS057H1F35I1HG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AS057K1F35E1HG
β Drop-Inβ In Stock
$1280 / Unit
View Datasheet β10AS057H2F34I1HG
β Drop-Inβ In Stock
$4980.3 / Unit
View Datasheet β10AS057K1F35I1HG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Core Processor | Dual ARM Cortex-A9 MPCore with CoreSight |
| Architecture | MCU, FPGA |
| Logic Elements | 570 K |
| Max Core Frequency | 1.5 GHz |
| User I/O Count | 396 |
| On-chip RAM | 256 KB |
| Package | 1152-FBGA, FC (35x35 mm) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | -40C to +100C (TJ) |
| Supplier Device Package | 1152-FBGA, FCBGA |
| Peripherals | DMA, POR, WDT |
| Connectivity | EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART |
| Process Node | 20 nm |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS057K1F35I1HG Pin Configuration
| Pin 1 | VCC β Core/IO supply voltage ball (multiple) |
| Pin 2 | VCCIO β IO bank supply voltage ball (multiple) |
| Pin 3 | GND β Ground ball (multiple) |
| Pin 4 | USER_IO β User IO ball (396 total, ball function multiplexed per Quartus pin assignment) |
| Pin 5 | XCVR_RX β Transceiver receive differential pair (multiple) |
| Pin 6 | XCVR_TX β Transceiver transmit differential pair (multiple) |
| Pin 7 | REFCLK β Transceiver reference clock input (multiple) |
| Pin 8 | DDR_DQ β DDR3/4 memory data ball (multiple) |
| Pin 9 | DDR_ADDR β DDR3/4 memory address ball (multiple) |
| Pin 10 | HPS_GPIO β Hard Processor System GPIO ball (multiple) |
| Pin 11 | CONFIG β FPGA configuration ball (MSEL, nCONFIG, nSTATUS, CONF_DONE) |
| Pin 12 | JTAG β JTAG balls (TCK, TMS, TDI, TDO, TRST) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K1F35I1HG is suitable for 7 applications: 5G Small-Cell Baseband Processing, Machine Vision and Industrial Inspection, Software-Defined Radio (SDR) Platforms, 4K Video Processing and Broadcast, Automotive ADAS Vision Pre-Processing, Medical Imaging Equipment, High-Performance Computing and Test & Measurement.
5G Small-Cell Baseband Processing
The 10AS057K1F35I1HG is well suited for 5G small-cell baseband because its 570K logic elements implement multi-antenna MIMO encoders/decoders, while the integrated Dual ARM Cortex-A9 MPCore subsystem runs the real-time MAC scheduler and L2/L3 protocol stack. The 12.5 Gbps multi-gigabit transceivers connect directly to radio front-end converters and to the backhaul Ethernet. SoC integration eliminates chip-to-chip latency between the ARM scheduler and the FPGA datapath, which is critical for sub-millisecond HARQ feedback in 5G NR TDD systems.
Recommended
Machine Vision and Industrial Inspection
Industrial machine vision systems benefit from the 10AS057K1F35I1HG's combination of FPGA fabric for pixel pipelines and ARM Cortex-A9 cores for vision software such as OpenCV-based defect detection. The DDR3/4 controller hard IP handles high-bandwidth camera sensor data (MIPI, LVDS, SLVS-EC), while the FPGA fabric performs real-time filtering, blob analysis and pattern matching at line rate. PCIe Gen3 connectivity supports integration with industrial PCs and frame grabbers.
Recommended
Software-Defined Radio (SDR) Platforms
The 10AS057K1F35I1HG powers high-end SDR platforms because its FPGA fabric executes wideband DDC/DUC, FFT, and channelization in real time, while the ARM Cortex-A9 subsystem runs waveform software, link-layer stacks, and network protocols. The integrated multi-gigabit transceivers up to 12.5 Gbps interface directly to wideband ADC/DAC front ends for sub-6 GHz and even mmWave applications via external mixers. This SoC FPGA collapses what used to be a multi-board DSP+FPGA+processor architecture into a single device.
Recommended
4K Video Processing and Broadcast
Broadcast video equipment uses the 10AS057K1F35I1HG for 4K/UHD real-time processing because the FPGA fabric handles pixel-rate operations (scaling, deinterlacing, color space conversion) at multi-gigapixel/s throughput. The ARM subsystem manages file I/O, network streaming, and control plane software. Integrated DisplayPort and HDMI support, plus PCIe for capture cards, make this SoC FPGA ideal for production switchers, contribution encoders and broadcast graphics systems.
Recommended
Automotive ADAS Vision Pre-Processing
ADAS vision systems leverage the 10AS057K1F35I1HG for sensor pre-processing because the FPGA fabric delivers deterministic low-latency pixel pipelines for camera, radar and lidar fusion. The Dual ARM Cortex-A9 MPCore subsystem executes perception middleware and object-tracking algorithms. Note that for full automotive qualification, designers should evaluate Arria 10 Auto-grade variants; the 10AS057K1F35I1HG industrial temperature range (-40C to +100C) accommodates many cabin and ADAS ECU thermal envelopes.
Recommended
Medical Imaging Equipment
The 10AS057K1F35I1HG is used in ultrasound, CT, MRI and endoscopy imaging systems because the FPGA fabric accelerates beamforming, image reconstruction and real-time filtering at high channel counts, while the ARM Cortex-A9 cores run the user interface, patient data management and DICOM networking. The deterministic timing of the FPGA pipeline is essential for medical-grade image quality, while the SoC integration reduces board space and BOM cost in compliance-constrained medical designs.
Recommended
High-Performance Computing and Test & Measurement
Test and measurement instruments - oscilloscopes, spectrum analyzers, protocol analyzers - leverage the 10AS057K1F35I1HG because the FPGA fabric performs real-time signal processing at the highest sample rates while the ARM subsystem runs the GUI, remote control protocols and data logging. The PCIe Gen3 interface connects to host CPUs, and the multi-gigabit transceivers handle high-speed serial protocol decoding for standards like USB 3.0, SATA and 10GbE.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K1F35I1HG β comparison, design guidance, and compliance information.
Selection Guide
Choose the 10AS057K1F35I1SG if you want the same die but a slightly different speed/option grade within the same F35 package - it remains a true drop-in replacement. Choose the 10AS057H1F35I1HG if your design needs lower DSP block count and cost is the primary driver. Choose the 10AS057K2F35E1HG when commercial-grade (0C to +100C) temperature is acceptable and you want the K2 option set. Avoid mixing 10AS (SoC) and 10AX (non-SoC) variants - their pinouts are not pin-compatible because the SoC parts reserve additional balls for the HPS subsystem.
Comparison with Alternatives
| Parameter | This Product | 10AS057K1F35I1SG | 10AS057K2F35I1HG | 10AS057K2F35E1HG | 10AS057H1F35I1HG | 10AS057K1F35E1HG |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA, FC (35x35 mm) | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX |
| Logic Elements | 570 K | 570 K | 570 K | 570 K | 570 K | 570 K |
| Speed/Option Grade | I1 (industrial, option set 1) | I1 (industrial, option set 1, SG variant) | I1 (industrial, option set 2) | E1 (commercial, option set 2) | I1 (industrial, H1 logic tier) | E1 (commercial, option set 1) |
| Operating Temperature | -40C to +100C (TJ) | -40C to +100C (TJ) | -40C to +100C (TJ) | 0C to +100C (TJ) | -40C to +100C (TJ) | 0C to +100C (TJ) |
| Core Processor | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore |
| User I/O Count | 396 | 396 | 396 | 396 | 396 | 396 |
Key Differentiators
- Dual ARM Cortex-A9 MPCore hard processor system on the same die (vs Arria 10 GX 10AX057K1F35I1HG (no HPS))
- 1152-FBGA package with 396 user I/Os (vs Arria 10 SX 10AS066N3F40E2SG (1517-FBGA))
- Industrial -40C to +100C operating range (vs 10AS057K2F35E1HG (commercial grade, 0C to +100C))
Design Notes
The 1152-FBGA FCBGA package requires a 1 mm ball pitch layout with at least 10 PCB layers. Per Intel Arria 10 SoC design guidelines, use a symmetric stackup with dedicated ground and power planes adjacent to the BGA breakout area. Fanout routing under the BGA should use micro-via (laser-drilled) or stacked-via technology to escape the inner ball rows without exceeding manufacturing constraints.
Estimated: at full FPGA fabric utilization (90% LE, all DSP blocks active, transceivers at 12.5 Gbps), the 10AS057K1F35I1HG dissipates approximately 15-20 W. With the 1152-FBGA package theta_JA around 12-15 C/W (typical for this package size with adequate PCB thermal vias), the junction temperature can rise 180-300 C above ambient. A heatsink or top-side cold plate is required for industrial temperature operation; route an array of thermal vias through the BGA land pad to the inner ground plane.
Do not confuse the Arria 10 SX SoC FPGA (10AS prefix, ARM HPS present) with the Arria 10 GX FPGA (10AX prefix, no ARM HPS). The pinouts differ because SoC variants reserve balls for the HPS subsystem. Always verify the exact ordering code against the Quartus Prime device library before PCB layout. Also confirm transceiver count and speed grade from the ordering code - they cannot be changed post-production.
DDR3/4 interfaces on the HPS subsystem require length-matched routing with controlled impedance (typically 50 ohm single-ended, 100 ohm differential for DQS). Use fly-by topology for clock signals and balance the byte lanes to within 5 ps. Place the DDR termination voltage (VTT) regulator close to the memory devices and decouple aggressively per the Arria 10 External Memory Interface Handbook.
Compliance Information
RoHS compliant and lead-free per Intel/Altera product listing at DigiKey. Operating temperature range -40C to +100C (TJ) supports industrial applications but part is not AEC-Q100 automotive qualified; for full AEC-Q100 consider Arria 10 Auto variants.
