10AS057K2F35E2LG - Arria 10 SX SoC FPGA 570K LE | Intel
MPN: 10AS057K2F35E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4252.63 | $4,252.63 |
| 10 | $4080 | $40,800.00 |
| 25 | $3890 | $97,250.00 |
| 100 | $3650 | $365,000.00 |
| 250 | $3450 | $862,500.00 |
Drop-in alternatives for 10AS057K2F35E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35E2SG
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View Datasheet →10AS057K2F35E1HG
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View Datasheet →10AS057K2F35E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 |
| Process Node | TSMC 20 nm |
| HPS Cores | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | 1.5 GHz |
| Transceivers | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | Gen3 x4 (rootport/endpoint) |
| User I/Os | 396 |
| Package | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | E2 (commercial/extended) |
| Operating Temperature | -40C to +100C (extended-industrial screening) |
| Configuration | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS057K2F35E2LG 1152-ball fcbga, 35 mm x 35 mm, 1.0 mm pitch Pin Configuration Guide
Complete pinout information for 10AS057K2F35E2LG (1152-ball fcbga, 35 mm x 35 mm, 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K2F35E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K2F35E2LG is suitable for 7 applications: Wireless Baseband and Radio Card, RADAR and Electronic-Warfare Signal Processing, Professional Video Broadcast and Studio, Industrial Machine Vision and Inspection, Test and Measurement Instrumentation, High-Performance Compute Accelerator Card, Medical Imaging and Diagnostic Equipment.
Wireless Baseband and Radio Card
The 10AS057K2F35E2LG is well suited to 4G/5G small-cell and macro baseband processing where a software control plane and a hardware-accelerated PHY must coexist on the same card. The dual ARM Cortex-A9 at 1.5 GHz runs the L2/L3 stack, OAM, and timing/sync protocols, while the 570K-LE fabric plus 17.4 Gbps transceivers handle LTE/NR channel coding, FFT/iFFT, and CPRI/eCPRI fronthaul at line rate. The 24 transceivers support CPRI rates up to 9.8 Gbps and 10G eCPRI over SFP+, with the PCIe Gen3 x4 hard IP bridging to a baseband SoC or backhaul switch.
Recommended
RADAR and Electronic-Warfare Signal Processing
For phased-array RADAR, ESM, and electronic-warfare systems, the 10AS057K2F35E2LG combines variable-precision DSP blocks for FFT, pulse compression, and DOA on every sample, with the HPS running classification, geolocation, and operator display. The -40C to +100C temperature screening makes the part directly deployable in ground-mobile and shipboard enclosures. The 24 multi-gigabit transceivers connect to ADC/DAC JESD204B/C lanes, while the PCIe Gen3 x4 hard IP links to a CPU/GPU co-processor for higher-level fusion.
Recommended
Professional Video Broadcast and Studio
Broadcast studios and outside-broadcast vans require uncompressed 4K/UHD-SDI processing, format conversion, and audio embedding in a compact, deterministic form factor. The 570K-LE fabric and the HPS cooperate to handle up to 12G-SDI ingest (with appropriate external SDI PHY), frame synchronization, color-space conversion, and HDR mapping. The HPS runs the control panel and network management, while the FPGA fabric handles real-time pixel processing at full frame rate, reducing host CPU load and enabling deterministic latency.
Recommended
Industrial Machine Vision and Inspection
Multi-camera factory inspection lines use the 10AS057K2F35E2LG to aggregate CoaXPress, Camera Link, or GigE Vision streams into the FPGA fabric for real-time image processing (defect detection, dimensional metrology, OCR) and into the HPS for line-level control and PLC integration. The 396 user I/Os drive lighting strobes, encoders, and reject solenoids, while the transceivers receive multi-gigabit vision data from multiple cameras simultaneously. Extended-industrial temperature screening supports deployment near process heat.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, protocol analyzers, and arbitrary waveform generators require deterministic DSP plus a flexible UI/processor. The 10AS057K2F35E2LG's 570K logic elements handle FFT, digital down-conversion, and trigger logic in real time, while the HPS drives the display, user interface, and remote control (LXI, SCPI). The 24 transceivers accept up to 17.4 Gbps serial data for protocol analyzers and high-speed serial bus compliance testing.
Recommended
High-Performance Compute Accelerator Card
FPGA-accelerator cards (HPC, AI inference, financial compute) plug into PCIe Gen3 x4 slots of servers and offload parallelizable kernels from the host CPU. The 10AS057K2F35E2LG's PCIe Gen3 hard IP, 570K-LE fabric, and dual Cortex-A9 cores deliver low-latency OpenCL/CUDA-to-FPGA acceleration, while DDR3/DDR4 with hard PHY on the FPGA domain provides large working-set memory for sparse algorithms. The HPS handles housekeeping and on-board management, keeping the host driver simple.
Recommended
Medical Imaging and Diagnostic Equipment
Ultrasound, CT, MRI, and endoscopy platforms use the 10AS057K2F35E2LG to drive transducer arrays or image sensors, perform beamforming/filtering/back-projection in the FPGA, and run the diagnostic UI on the HPS. The extended-industrial temperature range plus ECC-protected CRAM support hospital and lab environments. The 24 transceivers accept high-speed ADC data from the imaging front-end, while the 396 user I/Os drive display, keypads, and motor control for the gantry.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K2F35E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35E2SG | 10AS057K2F35E1HG | 10AS057K2F35I1HG | 10AS057K1F35I1HG | 10AS057K1F35E1HG | 10AS057H4F34I3LG |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F35, 35x35 mm) | 1152-ball FCBGA (F35, 35x35 mm) - same | 1152-ball FCBGA (F35, 35x35 mm) - same | 1152-ball FCBGA (F35, 35x35 mm) - same | 1152-ball FCBGA (F35, 35x35 mm) - same | 1152-ball FCBGA (F35, 35x35 mm) - same | 1157-ball FCBGA (F34, 35x35 mm) - same family |
| Logic Elements | 570,000 | 570,000 | 570,000 | 570,000 | 270,000 | 270,000 | 570,000 |
| Speed Grade | E2 | E2 (identical) | E1 (~15% Fmax lower) | I1 (~20% Fmax lower, industrial) | I1 | E1 | I3 (industrial) |
| HPS | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz - identical | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz |
| Process Node | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm |
| Operating Temperature | -40C to +100C | -40C to +100C | -40C to +100C | -40C to +100C | -40C to +100C | -40C to +100C | -40C to +100C |
| Approx. Qty-1 Unit Price (USD) | 4,252.63 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Pin-compatible lead-free second-source for second-source-ability (vs 10AS057K2F35E2SG)
- Same package, lower-cost speed-grade variants for cost-optimized designs (vs 10AS057K2F35E1HG)
- Industrial speed grade option for harsh-environment applications (vs 10AS057K2F35I1HG)
- Pin-compatible same-package lower-density alternative for low-utilization designs (vs 10AS057K1F35E1HG)
Design Notes
The 1152-ball FCBGA (F35, 35x35 mm, 1.0 mm pitch) requires an HDI PCB stack-up with laser-drilled microvias for the BGA break-out. Use a 1+N+1 or 2+N+2 build-up with at least four signal layers plus dedicated reference planes. Place decoupling capacitors on the bottom side of the PCB directly beneath their associated BGA balls using via-in-pad micro-via technology. For 17.4 Gbps transceivers, follow Intel's Arria 10 GX/SX Transceiver Layout Guidelines - route transceiver channels on stripline layers with controlled impedance (typically 100 ohm differential for transceivers, 85 ohm for CML interfaces) and avoid splitting the reference plane beneath transceiver channels.
Estimated: At maximum operating power (typical Arria 10 SX K2 device power ~25 W under heavy utilization), the 1152-ball FCBGA requires a forced-air heatsink or a cold-plate thermal solution. Use the Arria 10 PowerPlay Early Power Estimator (EPE) spreadsheet to compute junction temperature for your specific utilization profile; a typical 1 m/s airflow with 1 oz copper internal planes yields theta_JA of approximately 4-5 C/W. The thermal pad under the package should be soldered to the PCB thermal land and connected to an internal copper plane through an array of thermal vias.
A frequent mistake is treating the HPS boot sequence like a separate microcontroller - the Arria 10 SX HPS must boot BEFORE the FPGA fabric is configured if the FPGA design depends on HPS peripherals. Always configure the HPS boot source (NAND/NOR/SD/eMMC) in the Quartus HPS component and validate the preloader/U-Boot chain before releasing board files. Also enable SEU scrubbing and configuration CRC checking for any deployment where configuration memory corruption would be safety-relevant. Pin names in the HPS domain (HPS_* pins) are routed through the HPS-I/O block, not the FPGA fabric - do not assign them in the FPGA Pin Planner.
For DDR3/DDR4 interfaces on both the HPS and FPGA domains, use the Quartus Pin Planner to lock pin assignments to the recommended DQS grouping from the Arria 10 External Memory Interface Handbook. Length-match the byte lanes within +/- 10 mils of the DQS strobe, and length-match the address/command/control signals to a single fly-by topology. Enable on-die termination (ODT) and the dynamic phase-shift calibration engine; for DDR4 at 2133 MT/s, validate signal integrity with a 3D-EM solver (e.g., Ansys HFSS or Cadence Clarity) against the final PCB cross-section.
Power sequencing on the Arria 10 SX family is critical: the FPGA core VCC must reach its nominal voltage before the transceivers and HPS are powered up to avoid latch-up. Refer to the Arria 10 GX/SX Power Management User Guide - typically the recommended sequence is VCC (core) first, then VCCPT (periphery), then VCCP (transceivers/PLL), then VCCIO (I/O banks). Use a multi-rail PMIC such as the LTM4677 or EM21xx and program the rails with the Intel-recommended soft-start and ramp rates.
Compliance Information
RoHS-compliant and lead-free ball finish (LG suffix indicates Pb-free SAC405). AEC-Q100 not applicable - this is a high-density FPGA, not an automotive-grade IC. ECC-protected CRAM and extended-industrial temperature screening make it suitable for harsh-environment industrial, defense, and medical deployments but not for AEC-Q100 automotive use cases.
