EPC2LI20N - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
料号： EPC2LI20N ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.45 | $8.45 |
| 10 | $7.62 | $76.20 |
| 100 | $6.8 | $680.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.1 | $5,100.00 |
EPC2LI20N 概述
A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and serially shifts it into the FPGA during power-up or reconfiguration. The EPC2 belongs to the broader family of programmable read-only memory (PROM) -> serial configuration memory -> FPGA configuration devices -> memory ICs taxonomy. It uses a JTAG-driven in-system programmability model so designers can re-flash the configuration image on populated boards without removing the device, which dramatically simplifies field upgrades and debugging.
Key features include 1.6 Mbit Flash memory density, 20-pin PLCC (J-Lead) packaging, JTAG-based ISP, 3.0V/5.0V dual supply support, and a serial configuration clock rate up to 10 MHz. The device exposes standard Altera serial configuration signals (nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE) so it interfaces to legacy Altera FPGA configuration controllers without glue logic.
The EPC2LI20N uses a 4-pin serial interface to stream configuration data, with the FPGA acting as the configuration master. Internal oscillator and JTAG controller remove the need for external programming hardware, while in-system programming is supported via IEEE 1149.1 boundary scan. The result is a small-footprint, low-pin-count configuration solution that fits alongside the FPGA on the same PCB.
Typical applications include configuring Altera Cyclone series FPGAs in industrial controllers, Stratix II FPGAs in telecommunications line cards, and APEX II devices in DSP co-processing boards. It is also used in test and measurement equipment that requires field-updatable configuration.
When designing with this device, ensure the JTAG chain order is correct when multiple JTAG devices share the same TCK/TDI/TMS bus. The dual-supply design requires both 3.3V and 5V rails (or a single 3.3V rail with appropriate level shifting) to be present during configuration.
This page synthesizes distributor pricing, drop-in PLCC-20 alternatives from the Altera/Intel EPC family, and PCB-layout design notes not found in the manufacturer datasheet alone.
直接替换替代料： EPC2LI20N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPC2LI20N （相同外形与封装尺寸） ——差异在于 Memory Type, Mounting Type, Package, Supported FPGA Families, Interface.
快速对比工具——选择替代料号进行并排对比：
EPC2LC20N
✅ 直接替换✓ 有现货
$7.4 / 个
查看数据手册 →EPC2LC20
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPC2LI20
✅ 直接替换✓ 有现货
$5.95 / 个
查看数据手册 →EPC2LC22N
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EPC1LC20N
✅ 直接替换✓ 有现货
$8.4 / 个
查看数据手册 →EPC2LC21N
✅ 直接替换✓ 有现货
$10.95 / 个
查看数据手册 →EPC2LI20N 最大额定值与电气特性
| 存储器类型 | Non-volatile configuration PROM (Flash) |
| 存储容量 | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) |
| Configuration Mode | Serial |
| Maximum Configuration Frequency | 10 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V |
| 封装 / 外壳 | 20-PLCC (J-Lead), 9x9 mm |
| 安装类型 | Surface Mount |
| Packaging | Tube |
| Supported FPGA Series | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
EPC2LI20N 引脚配置
| 引脚 1 | DATA — Serial configuration data output to FPGA |
| 引脚 2 | DCLK — Serial configuration clock from FPGA |
| 引脚 3 | nCS — Chip select (active low) from FPGA |
| 引脚 4 | nCONFIG — Configuration control (active low) |
| 引脚 5 | nSTATUS — Configuration status (active low) |
| 引脚 6 | CONF_DONE — Configuration complete (active high) |
| 引脚 7 | TDI — JTAG test data in |
| 引脚 8 | TMS — JTAG test mode select |
| 引脚 9 | TCK — JTAG test clock |
| 引脚 10 | TDO — JTAG test data out |
| 引脚 11 | GND — Ground |
| 引脚 12 | OE — Output enable (active low) |
| 引脚 13 | VCCIO — I/O supply (4.5 V to 5.5 V) |
| 引脚 14 | VCCINT — Core supply (3.0 V to 3.6 V) |
| 引脚 15 | GND — Ground |
| 引脚 16 | NC — Not connected (per datasheet) |
| 引脚 17 | NC — Not connected (per datasheet) |
| 引脚 18 | NC — Not connected (per datasheet) |
| 引脚 19 | NC — Not connected (per datasheet) |
| 引脚 20 | NC — Not connected (per datasheet) |
典型应用
EPC2LI20N 适用于 6 应用s: Altera Cyclone FPGA Configuration, Stratix II Prototyping Boards, Industrial Motor Control Platforms, Telecommunications Line Cards, Test and Measurement Instrumentation, Legacy Board Repair and Field Service.
Altera Cyclone FPGA Configuration
The EPC2LI20N stores the configuration bitstream for Altera Cyclone series FPGAs (EP1C3, EP1C6, EP1C12, EP1C20) used in industrial control and DSP boards. The 1.6 Mbit density matches the bitstream size of EP1C3 through EP1C12 FPGAs; the 10 MHz serial configuration clock keeps FPGA initialization under 100 ms for these densities, and the JTAG ISP interface lets field engineers re-flash firmware without removing the device from the board.
推荐
Stratix II Prototyping Boards
In Stratix II (EP2S15, EP2S30) prototyping platforms the EPC2LI20N serves as a secondary configuration source for debugging and field updates. Although larger Stratix II devices typically use EPC4/EPC8/EPC16, the EPC2LI20N is a cost-effective option for EP2S15-class designs where 1.6 Mbit is sufficient. The dual 3.3 V/5 V supply interface allows direct connection to the Stratix II configuration pins without level shifters, simplifying PCB layout.
推荐
Industrial Motor Control Platforms
Variable-frequency drives and servo controllers built around Altera ACEX 1K or Cyclone FPGAs use the EPC2LI20N to store the field-oriented control (FOC) firmware bitstream. The industrial temperature grade (-40 C to +85 C) of the EPC2LI20N is well suited to factory-floor enclosures, and the JTAG ISP capability lets service technicians swap control algorithms without opening the drive cabinet. The 20-PLCC package is socket-compatible, simplifying field replacement.
推荐
Telecommunications Line Cards
Legacy telecom line cards based on Altera APEX II (EP2A15, EP2A25) FPGAs use the EPC2LI20N as a compact serial configuration source. The 9x9 mm 20-PLCC footprint fits dense line-card PCB layouts where board area is at a premium, and the JTAG interface enables remote bitstream updates via the card management controller. The 5 V VCCIO tolerance allows direct connection to APEX II multi-voltage configuration banks without level translation.
推荐
Test and Measurement Instrumentation
Oscilloscope, logic analyzer, and arbitrary waveform generator front-ends built on Altera Cyclone or Stratix II FPGAs use the EPC2LI20N to allow in-the-field firmware updates as new measurement algorithms are released. The JTAG ISP capability combined with 10 MHz serial configuration reduces product downtime during firmware upgrades, and the PLCC-20 socketable package simplifies board-level rework when the configuration PROM is replaced.
推荐
Legacy Board Repair and Field Service
The EPC2LI20N remains in active service for repairing legacy Altera FPGA boards in aerospace, defense, and industrial automation systems where board redesign is not cost-effective. Authorized franchised inventory has been constrained since the part was declared obsolete, but a healthy broker supply chain through distributors such as Heisener, WIN SOURCE, and TrustedParts.com keeps spares available as of 2026-09-11. Engineers should verify date code and lot traceability when sourcing through brokers.
推荐
推荐产品汇总
工程参考数据： EPC2LI20N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPC2LC20N | EPC2LC20 | EPC2LI20 | EPC2LC22N | EPC1LC20N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Package | 20-PLCC (J-Lead) 9x9 mm | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 0.5 Mbit (EPC1 family) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Configuration Clock | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Industrial temperature grade for harsh environments （对比 EPC2LC20N)
- 1.6 Mbit density matches Cyclone EP1C3-EP1C12 bitstreams （对比 EPC1LC20N)
- JTAG ISP enables field firmware updates （对比 EPC2LI20)
设计说明
The EPC2LI20N requires both VCCINT (3.0-3.6 V) and VCCIO (4.5-5.5 V) rails to be present and stable before the FPGA begins configuration. Power-sequencing VCCIO before VCCINT is recommended to avoid latch-up; decouple each supply pin with a 100 nF ceramic capacitor placed within 5 mm of the package, plus a 10 uF bulk capacitor on the VCCINT rail. Estimated: based on typical dual-supply PROM decoupling guidelines from the Altera EPC2 datasheet.
Route the JTAG signals (TCK, TDI, TMS, TDO) as a daisy-chain when multiple JTAG devices share the bus. Keep trace lengths matched within 25 mm and place a 10 kohm pull-up on TCK, TDI, and TMS to VCCIO to define the logic state during FPGA configuration. The nCONFIG/nSTATUS/CONF_DONE handshake signals should be pulled up to VCCIO with 10 kohm resistors and routed away from switching power converter nodes to avoid false triggering during power-up.
Do not exceed 5.5 V on VCCIO or 3.6 V on VCCINT; transient overshoot during hot-plug events can permanently damage the Flash cells. When programming in-system via JTAG, ensure the FPGA is not simultaneously driving DCLK or DATA, otherwise bus contention will corrupt the bitstream. Finally, verify the JTAG chain order matches the BSDL file before issuing the first PROG command to avoid inadvertently programming the wrong device.
合规信息
RoHS and REACH compliance status not explicitly stated in the verified web data; refer to the Altera/Intel FPGA PCN archive for the official compliance certificate. Part is not AEC-Q100 qualified - this configuration PROM is intended for industrial/commercial FPGA configuration, not automotive safety applications.
