W25Q128JVFIQ-TR - 128Mbit SPI/Quad NOR Flash, 16-SOIC | Winbond
料号： W25Q128JVFIQ-TR ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.62 | $16.20 |
| 100 | $1.38 | $138.00 |
| 500 | $1.18 | $590.00 |
| 1,000 | $1.05 | $1,050.00 |
| 3,000 | $0.95 | $2,850.00 |
W25Q128JVFIQ-TR 概述
A NOR flash memory is a non-volatile storage device that supports byte-level random read access and execute-in-place, meaning a microcontroller or SoC can fetch instructions directly from the flash array without copying them to RAM first. The W25Q family is built on Winbond's 3V SPI NOR process and offers a JEDEC-standard 25Q-series command set, making it interchangeable with other 25Q-compliant parts in firmware layers. It sits within the broader taxonomy of memory ICs -> non-volatile memory -> NOR flash -> SPI NOR flash, the most common code-storage medium for embedded MCUs, FPGAs, and boot ROMs.
Key features of the W25Q128JVFIQ-TR include 128M-bit density organized as 16M bytes, uniform 4 KB sectors with 32 KB and 64 KB block erase options for flexible memory management, a 256-byte page programming buffer, and a Quad SPI mode that delivers up to 133 MHz clock with single-, dual-, and quad-I/O data transfer. The device also includes a 3-byte (default) and 4-byte address mode for >128Mbit addressing, security registers with One-Time-Programmable (OTP) lockable bits, and a configurable QE bit (Status Register bit 9) for enabling quad I/O at boot.
The internal architecture combines a NOR memory array with a serial command decoder, an address counter, a 256-byte SRAM buffer, and the standard JEDEC 0x9F JEDEC-ID, manufacturer-ID, and device-ID registers. Continuous-read mode allows sequential read operations up to 133 MHz without command overhead, while the page-program and sector-/block-/chip-erase commands follow standard SFDP (Serial Flash Discoverable Parameters) discovery on JEDEC-compliant drivers.
Typical applications include firmware storage for STM32, ESP32, NXP i.MX RT, and Renesas RA microcontrollers, BIOS/Boot ROM on FPGA configuration stages, data logging on IoT sensor nodes, and asset tracking on smart-metering endpoints. The 133 MHz quad-SPI throughput also makes it suitable for display frame buffering on small TFT panels where boot-time code fetch matters.
When designing with the W25Q128JVFIQ-TR, ensure the SPI bus length is short (under 50 mm on standard FR-4) and that a 100 nF decoupling capacitor is placed within 5 mm of the VCC pin to limit switching noise. Note that quad-SPI XIP boot requires QE bit setup before the first quad command; firmware must program Status Register bit 9 once per reset to enable quad mode reliably.
直接替换替代料： W25Q128JVFIQ-TR ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： W25Q128JVFIQ-TR （相同外形与封装尺寸） ——差异在于 Block Erase Sizes, Memory Size, Memory Type.
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W25Q128JVFIQ
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| 存储器类型 | FLASH - NOR |
| Memory Format | Non-volatile |
| 存储容量 | 128 Mbit (16 MB / 16M x 8) |
| Memory Organization | 16M x 8 |
| 接口类型 | SPI, Dual SPI, Quad SPI, QPI |
| 最大时钟频率 | 133 MHz (Quad I/O) |
| Supply Voltage (VCC) | 2.7 V to 3.6 V |
| Active Read Current | 25 mA (typical at 133 MHz) |
| Standby Current | 15 uA (typical) |
| Sector Size | 4 KB uniform |
| Block Erase Sizes | 32 KB and 64 KB |
| Page Size | 256 bytes |
| 工作温度范围 | -40C to +85C (industrial) |
| Package Type | 16-SOIC (0.295 inch / 7.50 mm body width) |
| 安装类型 | Surface Mount |
| MSL 等级 | 3 |
| Packaging | Tape & Reel (TR) |
| RoHS 状态 | Compliant |
W25Q128JVFIQ-TR 引脚配置
| 引脚 1 | CS# — Chip Select (active low) |
| 引脚 2 | DO (IO1) — Serial Data Out / IO1 in Quad SPI mode |
| 引脚 3 | WP# (IO2) — Write Protect (active low) / IO2 in Quad SPI mode |
| 引脚 4 | GND — Ground |
| 引脚 5 | SI (IO0) — Serial Data In / IO0 in Quad SPI mode |
| 引脚 6 | SCK — Serial Clock |
| 引脚 7 | HOLD# / RESET# (IO3) — Hold / Reset (active low) / IO3 in Quad SPI mode |
| 引脚 8 | VCC — Power Supply (2.7V-3.6V) |
| 引脚 9 | NC — Not connected (per datasheet) |
| 引脚 10 | NC — Not connected (per datasheet) |
| 引脚 11 | NC — Not connected (per datasheet) |
| 引脚 12 | NC — Not connected (per datasheet) |
| 引脚 13 | NC — Not connected (per datasheet) |
| 引脚 14 | NC — Not connected (per datasheet) |
| 引脚 15 | NC — Not connected (per datasheet) |
| 引脚 16 | GND — Ground |
典型应用
W25Q128JVFIQ-TR 适用于 6 应用s: MCU Firmware Storage, FPGA Configuration Memory, IoT Sensor Data Logging, Smart Metering Endpoints, Industrial HMI Display Buffering, Asset Tracking and Wearables.
MCU Firmware Storage
The W25Q128JVFIQ-TR provides 16 MB of high-throughput SPI/Quad-SPI NOR flash for storing application firmware and bootloader code on 32-bit microcontrollers. Its 133 MHz quad-SPI clock and 4 KB uniform sectors make it ideal for execute-in-place (XIP) boot on STM32, ESP32, NXP i.MX RT, and Renesas RA families, where the MCU fetches code directly from the array without shadowing to RAM. The -TR tape-and-reel format supports automated SMT lines producing thousands of boards per day, and the 2.7V-3.6V supply matches 3.3V MCU rails without level shifters. Recommended companion MPNs: STM32H743VIT6, ESP32-S3-WROOM-1, ESP32-S3-WROOM-1, and ATSAM4S16C - all share quad-SPI peripheral blocks that map cleanly to the W25Q128JVFIQ-TR's standard JEDEC 25Q command set.
推荐
FPGA Configuration Memory
The W25Q128JVFIQ-TR serves as a configuration storage device for mid-range FPGAs from Xilinx (Spartan-7, Artix-7) and Lattice (ECP5, MachXO3), where multi-boot or remote-update capability is required. Its 133 MHz quad-SPI throughput comfortably exceeds the 100 MHz maximum configuration clock of these FPGAs, while the 16 MB capacity holds 2-3x typical bitstreams to support golden-image fallback and field OTA updates. The 16-SOIC package provides dedicated VCC/GND pin pairs that deliver low-noise power, and the HOLD#/RESET# pin allows Xilinx multi-PROG sequencing without external glue logic. Recommended companion MPNs: XC7A35T-1FTG256C, XC7S25-1FTGB196C, LFE5U-25F-8BG256C.
推荐
IoT Sensor Data Logging
The W25Q128JVFIQ-TR is well suited for buffering sensor data on battery-powered IoT nodes where local non-volatile storage survives deep-sleep cycles and grid outages. Its 15 uA typical standby current and 2.7V-3.6V supply fit coin-cell and Li-Ion platforms, while the 4 KB uniform sector allows time-stamped log segments to be erased without disturbing older entries. The 133 MHz quad-SPI throughput is rarely needed for logging, but the standard SPI mode running at 50 MHz easily handles burst writes from sensors sampling at kHz rates. Recommended companion MPNs: BME280 (environmental sensor), MAX17048 (fuel gauge), nRF52840 (BLE SoC with SPI).
推荐
Smart Metering Endpoints
Utility meters running on STM32 or NXP Kinetis platforms often use the W25Q128JVFIQ-TR to store firmware, calibration tables, and tamper-event logs over a 15-20 year service life. Its 100K endurance cycles per sector and 20-year data retention exceed typical utility-spec requirements, while the -40C to +85C industrial temperature range covers outdoor meter enclosures. The 16 MB capacity stores both the primary metrology image and a backup golden image, supporting secure firmware updates signed by the utility operator. Recommended companion MPNs: STM32L476RG, MK22FN512CAP12R.
推荐
Industrial HMI Display Buffering
The W25Q128JVFIQ-TR holds GUI assets, fonts, and partial frame buffers for small TFT HMI panels in industrial controllers and home appliances. Its 133 MHz quad-SPI mode pulls 8-16 MB of bitmap data into the LCD controller (e.g., RA8875, FT81x) within tens of milliseconds, supporting 5-7 inch panels with smooth refresh transitions. The -TR tape-and-reel format suits high-volume SMT lines producing consumer appliances, while the standard SPI command set eases driver porting across LCD controller families. Recommended companion MPNs: FT813, RA8875.
推荐
Asset Tracking and Wearables
Wearable fitness bands and asset-tracking tags use the W25Q128JVFIQ-TR to store GPS waypoints, activity logs, and firmware-upgrade staging areas in a tiny, low-power footprint. Its 4 KB sectors fit small log entries without wasting erase budget, and the standard SPI mode running at 25 MHz is sufficient for 1 Hz logging throughput. The 16-SOIC package is slightly larger than the WSON-8 alternative but offers easier hand-soldering for prototype runs, which is valuable in low-volume wearable development. Recommended companion MPNs: MAX32625, nRF52832.
推荐
推荐产品汇总
工程参考数据： W25Q128JVFIQ-TR ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | W25Q128JVFIQ | W25Q128JVSIQ | GD25Q128CSIG | GD25Q128CSIQ | IS25LP128-JBLE | MX25L12835FM2I-10G |
|---|---|---|---|---|---|---|---|
| Package | 16-SOIC | 16-SOIC (same) | 8-SOIC | 8-SOIC | 8-SOIC | 8-SOIC | 8-SOIC |
| Brand | Winbond | Winbond | Winbond | GigaDevice | GigaDevice | ISSI | Macronix |
| Density | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit |
| Voltage Range | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V |
| Max Clock (Quad I/O) | 133 MHz | 133 MHz | 133 MHz | 120 MHz | 120 MHz | 133 MHz | 104 MHz |
| Interface | SPI / Dual / Quad / QPI | SPI / Dual / Quad / QPI | SPI / Dual / Quad / QPI | SPI / Dual / Quad / QPI | SPI / Dual / Quad / QPI | SPI / Dual / Quad / QPI | SPI / Dual / Quad |
| Sector Size | 4 KB uniform | 4 KB uniform | 4 KB uniform | 4 KB uniform | 4 KB uniform | 4 KB uniform | 4 KB uniform |
| JEDEC ID | 0xEF (Winbond) | 0xEF (Winbond) | 0xEF (Winbond) | 0xC8 (GigaDevice) | 0xC8 (GigaDevice) | 0x9D (ISSI) | 0xC2 (Macronix) |
关键差异点
- Tape-and-reel packaging optimized for high-volume SMT lines （对比 W25Q128JVFIQ (tube version))
- Standard JEDEC 25Q command set ensures broad ecosystem compatibility （对比 GD25Q128CSIQ (GigaDevice))
- 133 MHz maximum quad-SPI clock rate （对比 MX25L12835FM2I-10G (Macronix))
设计说明
Place a 100 nF X7R ceramic decoupling capacitor within 5 mm of the VCC pin (pin 8) and a 10 uF bulk capacitor near the SOIC body. The W25Q128JVFIQ-TR draws up to 25 mA active during quad-SPI reads, so the VCC rail must be sized to avoid droop that triggers brown-out detection on the host MCU. Tie any unused NC pins (pins 9-15) to GND for cleaner EMI rather than leaving them floating.
Keep SPI bus traces under 50 mm total length on standard FR-4 to avoid reflections at 133 MHz clock. Use a 33 ohm series resistor near the SCK source to dampen ringing, and route CS#, SCK, IO0-IO3 as a length-matched group with 100 ohm differential impedance when using quad-SPI. Add a ground pour under the SOIC body to minimize EMI coupling from the high-speed quad-I/O bus.
The QE bit (Status Register bit 9) must be programmed before the first quad-I/O command, or the host will read incorrect data. In quad-SPI XIP boot flows, the bootloader must set QE once per reset using standard 0x01 write-status-register commands. Per the Winbond datasheet, the HOLD#/RESET# pin (pin 7) defaults to RESET# on power-up, so external pull-ups should not exceed 10 kohm to avoid false triggering during VCC ramp.
合规信息
RoHS compliant per Winbond datasheet. Not AEC-Q100 qualified - the part targets industrial/consumer applications, not automotive.
