FPGA & CPLD
Products (6352)
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
The Altera (now Intel) EPM7128EQI100-15 is a member of the MAX 7000 family of Complex Programmable Logic Devices (CPLDs), delivering 128 macrocells, 2.5K usable gates, and a 15 ns pin-to-pin propagation delay in a 100-pin PQFP package. The device operates from a 5 V supply and provides 84 user I/O pins, making it suitable for glue-logic, bus interfacing, and state-machine replacement tasks in industrial and telecom designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single die with a centralized interconnect fabric. CPLDs sit in the hierarchy between simple SPLDs and larger FPGAs, offering deterministic, fast pin-to-pin timing with instant-on behavior because configuration is stored in on-chip EEPROM rather than SRAM. The MAX 7000 family uses an EEPROM-based architecture, which means the device retains its programmed logic across power cycles without an external boot PROM, a notable advantage over SRAM-based FPGAs in cost-sensitive and safety-critical designs. Key features of the EPM7128EQI100-15 include 128 macrocells organized as 8 logic array blocks (LABs) of 16 macrocells each, a maximum operating frequency of approximately 76.9 MHz, programmable macrocell flip-flops, and a JTAG-compliant IEEE 1149.1 boundary-scan test interface. The "I" suffix in the part number denotes the industrial temperature grade of -40 °C to +85 °C, while the "E" designates the enhanced MAX 7000E variant. Each macrocell supports configurable clear, preset, clock, and output enable signals, allowing designers to implement combinatorial and registered logic in the same device. Typical applications include bus decoding and address mapping in microprocessor systems, I/O expansion for legacy ASICs, glue logic between modern processors and peripherals, board-level control sequencers, and small state-machine implementations. The 15 ns propagation delay comfortably supports standard 33 MHz PCI bus cycles and most asynchronous logic interfaces in industrial control hardware. When designing with this part, note that the EEPROM programming cycles are rated in the thousands, so the device is intended for prototyping or in-system updates rather than field-reprogrammable applications. Designers should also observe the 5 V VCC requirement and ensure decoupling complies with the Altera reference design to avoid noise-induced logic errors. This page synthesizes distributor pricing, drop-in speed-grade and temperature-grade alternatives, and engineering notes not found in the bare datasheet, providing a single source for engineers selecting a 5 V MAX 7000 CPLD for production builds.
EPM7128SLC84-10 - 128-Macrocell MAX 7000 CPLD | Intel
The Intel (formerly Altera) EPM7128SLC84-10 is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, housed in an 84-pin PLCC (J-lead) package. The device provides 128 macrocells, 2500 usable gates, and 68 user I/O pins, with a 10 ns pin-to-pin logic delay through the interconnect array. The 'S' suffix denotes in-system programmability via a built-in IEEE Std. 1149.1 JTAG interface plus 5.0V-tolerant I/O with MultiVolt support. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip, connected through a central programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between discrete PALs/GALs and larger FPGAs: they offer deterministic timing (typically predictable propagation delays), instant-on configuration from on-chip EEPROM, and moderate logic densities (hundreds of macrocells vs. millions of LUTs in modern FPGAs). The MAX 7000 family was Altera's second-generation MAX architecture and became the de-facto standard for glue-logic integration, bus interfacing, and state-machine consolidation in industrial and telecom designs from the mid-1990s through the 2000s. Key specifications include 128 macrocells (each containing a programmable AND/OR array plus one flip-flop), a maximum operating frequency of approximately 125 MHz for counter operation, a tPD (pin-to-pin delay) of 10 ns, and a tSU (setup time) of 7 ns. The device operates from a single 5.0 V supply (VCCINT = 4.75-5.25 V) with MultiVolt I/O supporting 2.5 V, 3.3 V, or 5.0 V mixed-voltage interfacing. The 84-pin PLCC package exposes 68 usable I/O plus JTAG and configuration pins. Internally, the MAX 7000S architecture uses four Logic Array Blocks (LABs) interconnected by a continuous programmable interconnect array (PIA). Each LAB contains 16 macrocells; each macrocell combines a programmable AND array, an OR/Exclusive-OR gate, a programmable flip-flop, and selectable clear/preset/clock control. Programming data is stored in on-chip EEPROM cells, allowing the device to retain its configuration indefinitely without external memory. The -10 speed grade indicates a 10 ns propagation delay. Typical applications include bus-interface bridging (e.g., 8/16/32-bit MCU-to-peripheral glue logic), address decoding and chip-select generation, state-machine consolidation in industrial controllers, and 5 V system glue logic in legacy telecom and factory-automation equipment. The -10 grade is the slowest of the three speed grades offered in this package (-7, -10, -15) and is therefore preferred when propagation delay is not timing-critical. When designing with this part, note that 84-pin PLCC sockets are widely available but require through-hole PCB footprint - plan for socket cost and assembly labor. Designers migrating legacy 5 V designs to 3.3 V MCUs often choose the MAX 7000S as the voltage-translation bridge because of its MultiVolt pinout. This page synthesizes distributor pricing, drop-in alternatives drawn from the MAX 7000S family, and practical design notes not found in the manufacturer datasheet.
EPM7128SLC84-10 - MAX 7000 CPLD, 128 Macro, 68 I/O, 10ns | Intel
The Intel (formerly Altera) EPM7128SLC84-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macrocells, 84 pins in a PLCC-84 (J-lead) package, and 68 user I/Os with a 10 ns pin-to-pin propagation delay. It is fabricated on a 5 V, EEPROM-based second-generation MAX architecture that delivers in-system programmability via the IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that bridges the gap between discrete glue logic and FPGAs. Within the broader taxonomy, the EPM7128SLC84-10 belongs to: CPLD -> PLD -> programmable logic -> digital semiconductor -> integrated circuit. It provides deterministic, fixed propagation delay across all 128 macrocells, making it ideal for glue-logic, bus interfacing, address decoding, and state-machine replacement. Unlike SRAM-based FPGAs, the EEPROM configuration cell retains the bitstream without external boot memory and powers up ready to operate. Key specifications include a maximum operating frequency of 125 MHz, 250 MHz internal frequency, 4.5 ns propagation delay (per the Alldatasheet index), and a maximum of 2500 usable gates. The device supports programmable speed/power optimization, allowing individual macrocells to run at reduced power with a small timing penalty. The 84-pin Plastic Leaded Chip Carrier (PLCC) package uses J-bend surface-mount leads suitable for socketed programming and production assembly. The MAX 7000S architecture employs a programmable interconnect array (PIA) that routes any macrocell output or I/O pin to any other macrocell input, providing full routability. Each macrocell contains a programmable AND/OR/flip-flop array with configurable clear, preset, clock, and output-enable controls. MultiVolt I/O pins permit interfacing with 2.5 V, 3.3 V, and 5 V logic without external level translation. The on-chip JTAG boundary-scan logic supports IEEE 1149.1 testing and in-system programming. Typical applications include bus interface bridging (e.g., 8/16/32-bit microprocessor glue logic), peripheral controller state machines, address decoding and chip-select generation, board-level reset sequencing, LED and seven-segment display multiplexing, and legacy industrial-control logic upgrades. Designers choose this part when deterministic timing, instant-on behavior, and single-chip simplicity outweigh the higher logic density of an FPGA. A primary design consideration is the 5 V VCC requirement; modern 3.3 V-only systems need a separate rail. JTAG chain ordering must keep TCK/TMS/TDO/TDI integrity when multiple devices share the boundary-scan bus. For new designs, verify the Altera/Intel MAX II or MAX V equivalent if lower power or 1.8 V support is required. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes drawn from the manufacturer MAX 7000 family datasheet and verified web sources.
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
The Intel / Altera EPM7128SLC84-15 is a 128-macrocell member of the classic MAX 7000S family of CMOS Complex Programmable Logic Devices (CPLDs), packaged in an 84-pin PLCC (J-Lead, J84) and rated for the -15 speed grade (tPD = 15 ns). The MAX 7000S family provides in-system programmability via IEEE Std. 1149.1 (JTAG), 5V tolerant I/O, and on-chip non-volatile EEPROM configuration memory, making the device a drop-in logic-integration solution for legacy industrial designs. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that sits between simple PAL/GAL devices and large SRAM-based FPGAs in the programmable logic hierarchy. CPLDs are typically used for glue logic, bus decoding, state-machine control, and I/O expansion because they offer deterministic timing, instant-on configuration (no boot PROM required), and predictable pin-to-pin delays across the whole device. Within that hierarchy, MAX 7000S is one of the longest-running Altera CPLD families, predating the modern MAX II / MAX V series. Key features of the EPM7128SLC84-15 include 128 macrocells (2,500 usable gates), 68 user I/Os in the 84-pin PLCC footprint, a maximum internal operating frequency of up to 76.9 MHz (the -15 speed grade supports roughly 125 MHz fMAX in commercial temperature), and 4.5 ns propagation delay per pin as reported on third-party datasheet mirrors. The device is built on a 5V-tolerant CMOS EEPROM process and supports multi-volt I/O for interfacing with 3.3V and 5V logic. Programming is performed through the built-in JTAG port using Quartus or MAX+PLUS II toolchains. Typical applications include industrial PLC and process-control glue logic, telecommunications backplane bus bridges, address decoding and wait-state generation in legacy x86 embedded systems, and ASIC-prototype logic replacement. The 84-PLCC package makes the part attractive for socketed legacy boards and field-replacement scenarios. When designing with this device, ensure that the JTAG chain is correctly ordered if multiple devices are cascaded, and observe the I/O bank's 5V VCCIO requirement when interfacing with legacy TTL logic. The instant-on EEPROM configuration is a key advantage over SRAM-based FPGAs in safety-critical systems. This page synthesizes distributor pricing, drop-in alternatives within the same MAX 7000 family, and practical design notes that are not consolidated in any single manufacturer datasheet.
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
The Intel (Altera) EPM7128SLC84-6N is a high-performance CMOS CPLD from the MAX 7000S family, delivering 2.5K system gates, 128 macro cells, and 68 user I/Os in an 84-pin PLCC (J-lead) package. Operating at 5V with a 6 ns pin-to-pin delay, this device targets glue-logic, bus-interface, and state-machine applications where deterministic timing and in-system programmability (ISP) are essential. It is built on EEPROM process technology and is fully compatible with the legacy MAX+PLUS II / Quartus toolchains for bitstream generation and JTAG-based programming. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/PLA architectures with the density and macro-cell flexibility of modern FPGAs. Within the broader programmable-logic taxonomy, the CPLD sits between simple SPLDs (PALs/GALs) and high-density SRAM-based FPGAs, offering instant-on behavior (no external boot PROM required) and predictable propagation delays that simplify timing closure for control-plane logic. The MAX 7000S series is one of the industry's longest-lived CPLD families, valued for its low power consumption, 5V tolerance, and ability to absorb wide glue-logic functions into a single package. Key features of the EPM7128SLC84-6N include 128 macro cells (each containing 16 product terms), 2500 usable system gates, an fMAX of 147.1 MHz, four dedicated inputs (for high-speed clocking), two global clocks, and JTAG-compliant IEEE 1149.1 boundary-scan support. The 6 ns speed grade represents one of the fastest bins in the MAX 7128 family, making it suitable for memory-interface controllers, address decoding, and peripheral glue where sub-10 ns response is required. Typical applications include ISA/PCI bus interface logic, peripheral address decoding, microcontroller I/O expansion, state-machine-based control, and legacy 5V industrial systems. The non-volatile EEPROM cell array eliminates the need for external boot memory, supporting instant-on configuration at power-up. Designers should note that the EPM7128SLC84-6N is a legacy part approaching end-of-life for new designs; production volumes continue for maintenance, but long-term availability for new programs should be confirmed via distributor channels. Pin-compatible speed-grade variants (EPM7128SLC84-7, -10, -15) and identical-die QFP packages (EPM7128SQC100, EPM7128BTC100) exist for design flexibility. This page synthesizes drop-in alternative listings, parametric comparisons against same-family MAX 7000S variants, and practical design notes (power sequencing, ISP/JTAG usage, 5V mixed-signal considerations) that go beyond the basic datasheet summary, helping engineers sourcing, replacing, or re-spinning legacy MAX 7000S designs.
EPM7128SLC84-7N - 128 Macro Cell 7.5ns MAX 7000S CPLD | Intel
The Intel (formerly Altera) EPM7128SLC84-7N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 128 macro cells and 2,500 usable gates in an 84-pin PLCC (J-lead) surface-mount package. The device is specified at the -7 speed grade with a maximum pin-to-pin propagation delay (tpd) of 7.5 ns and a maximum operating frequency of 125 MHz, supporting 5V core operation from a 4.75 V to 5.25 V supply rail. A Complex Programmable Logic Device (CPLD) is a non-volatile, in-system programmable logic IC that bridges the gap between discrete logic gates and full FPGAs. CPLDs use EEPROM or flash memory cells to store their configuration, retaining bitstream through power cycles without external boot memory. Architecturally, CPLDs belong to the programmable logic hierarchy (CPLD -> PLD -> programmable logic -> digital IC -> semiconductor) and are typically deployed for glue logic, bus bridging, state-machine control, and I/O expansion where deterministic timing and instant-on behavior matter more than raw logic density. Key features of the EPM7128SLC84-7N include 128 macro cells organized into 8 logic array blocks (LABs), 68 user I/O pins, in-system programmability (ISP) via JTAG, and counter speeds up to 175.4 MHz on faster speed grades. The MAX 7000S second-generation MAX architecture integrates a programmable interconnect array (PIA) that routes signals between LABs with predictable timing, eliminating the routing-variation problem of early PLDs. Built on advanced CMOS EEPROM technology, the device offers 100% TTL-compatible I/O and supports hot-socketing for legacy bus designs. Typical applications include 5V bus-interface glue logic in industrial control boards, address decoding and interrupt steering in embedded motherboards, legacy peripheral replacement for 74LS/74F TTL logic, state-machine controllers for motor drives, and I/O expansion around microcontrollers and DSPs. The wide 5V tolerance also makes it suitable for prototyping legacy PC/104 and VMEbus systems. When designing with this device, ensure that the JTAG pins (TDI, TDO, TMS, TCK) are properly terminated and that the input ramp time on VCC respects the EEPROM programming requirements. The 84-pin PLCC package requires a socket or hand-soldered footprint; for new designs consider the modern MAX II or MAX V equivalent. Power dissipation scales with the toggle rate of the programmed logic and the output loading.
EPM7128SLI84-10 - MAX 7000 CPLD 128MC 10ns 84-PLCC | Intel
The Intel (formerly Altera) EPM7128SLI84-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2.5K usable gates, 128 macro cells, and 68 user I/Os in a 84-pin Plastic Leaded Chip Carrier (PLCC) package. It operates at 100 MHz internal frequency with a 10 ns pin-to-pin propagation delay, and is built on a 5 V CMOS technology node with EEPROM-based configuration memory that is in-system programmable (ISP) via JTAG. The SLI suffix indicates the industrial operating temperature range of -40 °C to +85 °C, while the -10 speed grade denotes a 10 ns tPD. The device is organized as 8 Logic Array Blocks (LABs) of 16 macro cells each, interconnected by a programmable interconnect array (PIA) shared with the I/O control blocks. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the architectural simplicity of a PAL/GAL with the density and flexibility of an FPGA for glue-logic, bus-interface, state-machine, and control-plane tasks. In the digital-system hierarchy, CPLDs sit between discrete 74-series glue logic and full FPGAs: they offer deterministic timing, instant-on from non-volatile memory, and pin-to-pin delays of a few nanoseconds - making them ideal for deterministic control logic rather than parallel data-path processing. The MAX 7000S family specifically targets 5 V system designs and remains a long-lived platform for industrial and legacy upgrades. Key features include 128 macro cells, 68 available user I/Os, JTAG boundary-scan support compliant with IEEE Std 1149.1, multi-voltage I/O (5.0 V core with 3.3 V or 5.0 V interface), open-drain or totem-pole output options per pin, and programmable power-saving mode per macro cell. The 84-pin PLCC package provides through-hole or socket compatibility for legacy boards, while the in-system programmability via the ByteBlaster or ByteBlasterMV cable eliminates the need for a separate programmer. Typical applications include 5 V industrial control boards, ISA/PCI bus-interface glue logic, address decoding, state-machine controllers, and legacy microprocessor peripheral interfaces where deterministic 10 ns timing and instant-on from EEPROM configuration are required. When designing with this part, plan for the 5 V VCCINT requirement and consider the EPM7128SLI84-10N lead-free variant if RoHS compliance is mandatory for new designs. This page synthesizes distributor pricing, drop-in 84-PLCC alternatives, and practical design notes not found in the original Altera datasheet.
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
The Intel / Altera (formerly Altera Corporation) EPM7128SLI84-10N is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2,500 usable gates and 128 macro cells with 68 user I/Os in a 84-pin Plastic Leaded Chip Carrier (PLCC) package. The "-10N" speed grade specifies a pin-to-pin propagation delay (tPD) of 10 ns, and the device is built on EEPROM process technology for non-volatile in-system programmability. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the instant-on, deterministic timing characteristics of PAL/GAL architecture with macro-cell granularity typically ranging from 32 to 512 cells. CPLDs sit in the programmable logic hierarchy between simple SPLDs (PAL/GAL) and larger FPGAs, and are typically used for glue logic, bus interfacing, state-machine control, and decoder functions where deterministic 5-15 ns pin-to-pin delays and high fan-in logic replacement matter more than raw register count. Key features of the EPM7128SLI84-10N include a maximum toggle frequency of 125 MHz, JTAG-compliant IEEE Std 1149.1 boundary-scan support, an I/O bank that is 5 V tolerant with 3.3 V or 5 V core operation, and four pin-compatible "-10/-12/-15/-20" speed grades in the same PLCC-84 footprint. The MAX 7000S architecture provides 100% factory-tested logic and supports MultiVolt I/O for interfacing to 2.5 V, 3.3 V, and 5 V devices on the same board. An internal 3.3 V regulator (when powered from 5 V) reduces active power by approximately 50% compared with the original MAX 7000 family. Architecturally, the device is organized as 16 Logic Array Blocks (LABs), each containing 16 macro cells, interconnected by a continuous Programmable Interconnect Array (PIA). Each macro cell contains a programmable AND/OR array, a configurable flip-flop, and per-cell product-term allocation. The EEPROM-based non-volatile configuration stores the bitstream on-chip, eliminating external boot memory and enabling instant-on behavior at power-up - a key advantage over SRAM-based FPGAs. Typical applications for the EPM7128SLI84-10N include bus-interface glue logic (PCI, ISA, VME), address decoding and chip-select generation, state-machine controllers, peripheral I/O expansion, and legacy 5 V system replacement. Designers frequently choose this part when migrating from discrete 74-series TTL or from PAL/GAL devices where higher density or in-system reprogrammability is needed. A key design consideration when using the EPM7128SLI84-10N in a new board design: modern designs targeting the PLCC-84 footprint should plan for the part's mature (last-time-buy / NRND) lifecycle status and consider pin-compatible MAX II or MAX V devices for new production. For legacy designs where PCB rework is not feasible, the EPM7128SLI84-10N remains the pin-compatible drop-in solution. Design with proper decoupling (one 0.1 uF + one 10 uF per VCC/ GND pair) and follow Altera AN 74 (MAX 7000 in-system programmability) for ISP-friendly JTAG chains. This page synthesizes distributor pricing, drop-in alternatives within the PLCC-84 footprint, and practical design notes not found in the manufacturer datasheet alone.
EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel
The Altera (Intel) EPM7128SLI84-15 is a 128-macrocell EE PLD from the MAX 7000 programmable logic family, delivering 15 ns pin-to-pin propagation delay in a 84-pin PLCC (J-lead) package. It operates from a single 4.5 V to 5.5 V supply and supports configurable I/O standards at 3.3 V or 5 V, enabling mixed-voltage interfacing with both legacy TTL and modern low-voltage CMOS logic. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that implements glue logic, bus interfacing, state machines, and address decoding through AND/OR arrays of macrocells. Within the broader hierarchy, CPLD -> programmable logic device (PLD) -> programmable logic IC -> logic semiconductor. Compared with FPGAs, CPLDs typically have lower logic density but deterministic timing, lower power, and instant-on behavior from on-chip EEPROM, which makes them ideal for control-plane rather than data-plane functions. Key features include 128 macrocells, 84 user I/O pins, a 15 ns propagation delay (tpd) at the commercial speed grade, and in-system programmability via the JTAG-compliant IEEE Std 1149.1 interface. The MAX 7000S architecture uses EEPROM process technology, allowing the configuration to be re-programmed in-circuit up to 100 times and retained for 20 years, eliminating external boot PROMs. The architecture combines a programmable interconnect array, macrocells with product-term-based logic synthesis, and programmable I/O cells that support 3.3 V or 5.0 V output levels. Each macrocell contains a programmable AND/OR array feeding a configurable flip-flop, and the I/O block can be set per-pin to input, output, or bidirectional mode. This makes the part a flexible bridge between processors, memories, and peripherals. Typical applications include bus address decoding and chip-select generation, glue logic between microprocessors and peripherals, state-machine control in industrial automation, peripheral interface bridging (PCI, ISA, VME), and post-PCB redesign fixes for digital logic that has already been laid out. The wide 5 V tolerance and 84 PLCC pins support legacy backplane designs where many control signals must be aggregated. When designing with this device, ensure that the JTAG chain order matches the BSDL file and that all unused I/O pins are left floating or tied to GND through a weak pulldown, per Altera application notes. The PLCC-84 socket must be a through-hole or socketed type if field upgrades are expected; for high-vibration environments a press-fit socket is recommended.
EPM7128SQC100-10 - MAX 7000S CPLD, 128 Macro, 84 I/O | Altera
The Altera (Intel) EPM7128SQC100-10 is a high-density, high-performance Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macrocells, 2,500 usable gates, and 84 user I/O pins in a 100-pin PQFP (Plastic Quad Flat Pack) package. It is built on a 5V CMOS process with a 10 ns pin-to-pin logic delay, making it one of the most widely deployed 5V CPLDs in industrial glue-logic, bus-interface, and legacy replacement designs. What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-on programmable logic device that sits between simple PAL/GAL devices and larger FPGAs. It uses an EEPROM- or flash-based architecture to retain configuration without a boot PROM, offers predictable timing with deterministic pin-to-pin delays, and is typically used for glue logic, address decoding, state-machine control, and bus-interface bridging. Within the programmable-logic hierarchy (PAL/GAL < CPLD < FPGA), the MAX 7000S family represents a mature, cost-effective tier for 5V systems. Key features include a 100 MHz maximum operating frequency, in-system programmability (ISP) via JTAG, programmable macrocell flipflops with individual clear, preset, clock, and clock-enable controls, open-drain output option, and pin compatibility with the wider MAX 7000S family. The device supports 5V core and I/O operation, with I/O pins tolerant of mixed-voltage interfacing. The EPM7128SQC100-10 uses a second-generation MAX architecture with a global interconnect fabric linking 16 Logic Array Blocks (LABs), each containing 8 macrocells. This architecture delivers fast, deterministic propagation delays that are critical for synchronous designs where setup/hold margins must be calculated precisely. The 100-pin PQFP package provides a low-cost, easy-to-inspect footprint for through-hole-style prototyping and rework. Typical applications include address decoding and bus interfacing for microprocessors and microcontrollers, glue logic between ASICs and standard peripherals, state-machine control in industrial controllers, legacy 5V system upgrades from discrete 74LS/74HC logic, and peripheral expansion for legacy parallel-port designs. Designers also use the EPM7128 family for I/O voltage translation and timing adjustment in mixed-voltage boards. When designing with this part, treat the 10 ns speed grade as the timing baseline: any design migrated from a faster grade (e.g., -6 or -7) must be re-checked for setup/hold at the new tPD. Decoupling requires 0.1 uF and 10 uF bulk caps near VCC pins, and unused JTAG TCK pins should be tied to GND through 1 kohm in noisy environments. This page synthesizes distributor pricing, drop-in alternatives (EPM7128SQC100-7, EPM7128SQC100-15N, EPM7128SQC100-10N), and practical design notes not found in the manufacturer datasheet alone, helping engineers shorten the selection and qualification cycle for legacy and 5V-tolerant designs.
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
The Altera (Intel) EPM7128SQC100-10F is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2,500 usable gates, 128 macrocells, and 84 user I/Os in a 100-pin Plastic Quad Flat Pack (PQFP) with a 10 ns pin-to-pin delay. The part is fabricated on advanced EEPROM-based process technology and operates from a single 5 V supply, providing in-system programmability (ISP) through a standard 4-pin JTAG interface (IEEE Std 1149.1). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style logic blocks (called macrocells or logic array blocks) on a single chip with a centralized programmable interconnect. Within the broader taxonomy, a CPLD sits below an FPGA in logic density but above a simple SPLD/PAL in functional integration, making it ideal for glue logic, bus interfacing, and control-plane state-machine tasks in mixed-signal systems. The MAX 7000S family specifically targets 5 V designs and offers deterministic, nanosecond-range timing that simplifies timing closure for asynchronous interfaces. Key features of the EPM7128SQC100-10F include counter frequencies up to 100 MHz, eight pin- or global-clock-driven logic array blocks, programmable power-saving mode that reduces each macrocell I/O current to a few microamperes, and individual macrocell register clear, preset, clock, and clock-enable controls. The 5 V tolerant I/O and 10 ns tPD make this part a long-standing choice for legacy industrial and telecommunications designs where noise margins and timing predictability matter more than raw gate count. Architecturally, the device uses a second-generation MAX architecture with a uniform interconnect that routes signals between LABs through a fast, predictable switch matrix. The non-volatile EEPROM cells retain configuration without external memory, allowing the device to behave as a standalone logic component on power-up with no boot time, which is critical for control-plane glue logic and bus-bridge designs. Typical applications include 5 V glue logic and bus interfacing (ISA, PCI, VME bridges), peripheral control for microcontrollers, address decoding and chip-select generation, state-machine and sequencer logic in industrial automation, telecommunications backplane glue, and legacy replacement for discrete 74-series TTL/CMOS logic on production boards. The 100-PQFP package also remains common in long-lifecycle industrial and aerospace designs. When designing with this part, confirm that 5 V tolerance is acceptable for downstream I/O banks; the 100-PQFP footprint is also offered in a -10N lead-free variant (EPM7128SQC100-10N) for RoHS-only builds. The 'F' suffix denotes a lead-free (Pb-free) finish, making the EPM7128SQC100-10F suitable for modern RoHS-compliant assembly while maintaining 5 V core operation. This page consolidates distributor pricing, in-system programming guidance, drop-in same-package alternatives (including the lead-free N-suffix and automotive I-suffix variants), and practical design notes not aggregated on the manufacturer datasheet cover page.
EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
The Altera EPM7128SQC100-10N is a high-density, high-performance CMOS CPLD (Complex Programmable Logic Device) from the MAX 7000 family, featuring 128 macro cells, 2,500 usable gates, and a 100-pin PQFP (Plastic Quad Flat Pack) package with 10ns pin-to-pin logic delay and 100 MHz internal operating frequency at 5V supply. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of a PAL (Programmable Array Logic) with the density of an FPGA. CPLDs occupy a position in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic -> semiconductor. They are valued for their deterministic timing, instant-on non-volatile configuration (EEPROM-based in the MAX 7000 family), and low power consumption, making them ideal for glue logic, bus interfacing, and state-machine implementation in industrial, telecommunications, and embedded systems. Key features of the EPM7128SQC100-10N include 128 macro cells organized as 8 Logic Array Blocks (LABs) of 16 macro cells each, 84 user I/O pins, 5V core supply with 3.3V or 5V I/O compatibility via MultiVolt interface, in-system programmability (ISP) via the JTAG-compliant 4-pin IEEE Std. 1149.1 interface, and 10ns combinatorial propagation delay (tPD). The MAX 7000 architecture is built on Altera's second-generation MAX architecture with EEPROM configuration memory. From a technical depth perspective, the MAX 7000 family uses a programmable interconnect array (PIA) that routes signals between LABs without contention, and each macro cell contains a programmable AND/OR array, a product-term select matrix, and a configurable flip-flop. The device supports JTAG boundary-scan testing per IEEE 1149.1 and includes built-in test logic for board-level verification. The 100-pin PQFP package has a body size of approximately 20 x 14 mm with 0.65 mm pitch gull-wing leads. Typical applications include industrial control glue logic, address decoding and bus interfacing in embedded systems, state machines for motor control, peripheral interfacing in telecommunications equipment, and legacy 5V system designs where FPGAs are overkill. The wide operating voltage tolerance (4.75V to 5.25V) also supports -40C to +85C industrial temperature range operation. When designing with this device, ensure the JTAG chain is properly terminated to avoid programming failures, and use the Quartus Prime or MAX+PLUS II software for design entry, synthesis, and programming file generation. Power sequencing should maintain VCC within specification before JTAG operations to prevent partial configuration. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
The Altera (now Intel) EPM7128SQC100-15 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, providing 128 macrocells, 84 user I/Os, and a 15 ns pin-to-pin logic delay in a 100-pin PQFP package. It operates from a 5 V supply (5% tolerance) and supports in-system programmability through the IEEE Std. 1149.1 (JTAG) interface and a built-in Altera MasterBlaster or ByteBlaster programming path. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays on a single die with a global interconnect fabric. The MAX 7000 family is Altera's second-generation EEPROM-based CPLD architecture, positioned between simple PLDs and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA. MAX 7000 parts retain configuration in on-chip EEPROM, so they boot instantly at power-up without an external configuration PROM - an advantage over SRAM-based FPGAs in deterministic-startup applications. Key features of the EPM7128SQC100-15 include 128 macrocells organized into 4 Logic Array Blocks (LABs), a 2,500-gate typical density, 84 user I/O pins, programmable power management with macrocell-level slew-rate control, and a 15 ns tPD (worst-case pin-to-pin delay) suitable for 66 MHz operation. The device also provides 4 dedicated inputs, 6 to 10 product terms per macrocell, and a JTAG boundary-scan test interface compliant with IEEE 1149.1. The architecture uses Altera's classic MAX (Multiple Array matriX) interconnect, with each LAB containing 16 macrocells feeding a Programmable Interconnect Array (PIA). This structure delivers fast, predictable combinational and registered logic delays that are independent of routing density - a key reason MAX 7000 CPLDs remain in long-life programs where deterministic timing matters more than raw density. Typical applications include bus-interface glue logic, peripheral decoders and address mapping, state-machine control in industrial automation, board-level signal conditioning in telecom backplanes, and pin-compatible upgrades for legacy 5 V TTL/CMOS designs. The 5 V tolerance and PQFP-100 footprint also make it a common choice for maintenance of installed equipment in factory automation and aerospace ground systems. When designing with this part, plan for an external 5 V regulator with at least 200 mA headroom and follow Altera's JTAG chain layout guidelines (TCK pull-down, TMS/TDI pull-ups) to avoid programming failures. Note that the EPM7128SQC100-15 is a mature / legacy product; verify lifecycle status before new designs. This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 7000 / MAX 7000A families, and practical design notes not found in the manufacturer datasheet itself.
EPM7128SQC100-6 - 128-Macrocell MAX 7000S CPLD, 5V | Intel
The Intel (formerly Altera) EPM7128SQC100-6 is a 128-macrocell member of the classic MAX 7000S family of complex programmable logic devices (CPLDs), fabricated on a 5V CMOS EEPROM process and packaged in a 100-pin PQFP (SQC). The device integrates 2,500 usable gates and 128 macrocells with 84 user I/O pins, providing non-volatile, instant-on logic with 6 ns pin-to-pin propagation delay and an internal frequency up to 147.1 MHz. It supports in-system programmability (ISP) via the IEEE 1149.1 JTAG interface and 5V tolerant I/Os, making it suitable for legacy glue-logic, bus-interface, and state-machine replacement designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip, connected through a programmable interconnect matrix (PIA). CPLDs sit between simple PLDs and FPGAs in the programmable logic taxonomy: PLD -> CPLD -> FPGA -> programmable logic -> semiconductor. Unlike SRAM-based FPGAs, CPLDs retain their configuration without external memory and offer deterministic, sub-10 ns timing that engineers can rely on for asynchronous glue logic, decoder replacement, and bus-interfacing tasks. The MAX 7000S architecture implements each macrocell with a programmable product-term array, a programmable register (D/T/JK/SR flip-flop), and a tri-state output buffer. With 128 macrocells the device delivers up to 6.25 ns combinational propagation and 147.1 MHz internal operation; the -6 speed grade specifies a maximum 6 ns pin-to-pin delay. MultiVolt I/O supports interfacing with 3.3V and 5V mixed-voltage systems. ISP via JTAG allows field upgrades, while the 100-pin PQFP provides ample I/O density for bus bridges, peripheral controllers, and industrial glue logic. Typical applications for the EPM7128SQC100-6 include PCI/local-bus interface bridges, peripheral glue logic in 5V industrial systems, JTAG-controlled scan and boundary-test fixtures, address decoding and interrupt management in embedded motherboards, and legacy designs migrating discrete 74LS/74HC logic into one programmable device. Its instant-on, deterministic timing and 5V tolerance make it a common choice in industrial and telecom platforms where 3.3V-only FPGAs are not suitable. When designing with the EPM7128SQC100-6, ensure 5V-tolerant I/O banks are configured to match downstream logic levels; use a 100-pin PQFP land pattern with sufficient copper area for thermal dissipation; and program via Quartus II or the legacy MAX+PLUS II toolchain using the JTAG chain defined in the datasheet. Always respect the device's 5V VCCIO absolute maximum and decouple VCC pins with 0.1 uF ceramic capacitors close to the package. This page synthesizes distributor stock and pricing for EPM7128SQC100-6, MAX 7000S family drop-in speed-grade and package alternatives (EPM7128SQC100-7, -10, -15, -10N, -10F) that share the same 100-pin PQFP footprint, and practical design notes not consolidated in the manufacturer datasheet.
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
The Altera (now Intel) EPM7128SQC100-7 is a high-density, 5V, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 128 macro cells, 84 user I/O pins, and a 7.5 ns pin-to-pin propagation delay in a 100-pin Plastic Quad Flat Pack (PQFP) package. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that sits between discrete glue-logic ICs and larger FPGAs. Within the broader semiconductor taxonomy, the EPM7128SQC100-7 belongs to the CPLD category -> programmable logic -> digital IC -> semiconductor. MAX 7000S devices use a classic EEPROM-based architecture, providing deterministic timing, infinite reconfigurability (over 100 program/erase cycles), and 100% non-volatile storage so designs power up in a known state without external boot memory. Key features include 2,500 usable gates, a maximum internal operating frequency of 125 MHz (with some sources citing up to 250 MHz internal), 5.0V VCCIO/VCCINT operation, in-system programmability through a standard 4-pin JTAG interface (IEEE Std 1149.1), and built-in support for the MAX+PLUS II and Quartus development flows. The device includes 128 macro cells, each composed of a programmable AND/OR array feeding a configurable flip-flop, and provides flexible I/O standards including TTL and CMOS. Architecturally, the EPM7128SQC100-7 organizes its 128 macro cells into four Logic Array Blocks (LABs) interconnected through the Programmable Interconnect Array (PIA). This matrix-based interconnect delivers predictable, fixed-delay signal routing - a key advantage over SRAM-based FPGAs for deterministic glue-logic, bus-interface, address-decoding, and timing-critical applications where race conditions must be eliminated. Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microprocessor glue logic), address decoding and chip-select generation, state-machine controllers, peripheral interface expansion, and legacy 5V system designs that require non-volatile, instantly-on logic. The 84 available user I/Os accommodate wide parallel buses and multi-channel control logic. When designing with this device, plan for a single 5V supply rail and verify that total output loading plus simultaneous switching I/O does not exceed the thermal envelope. For new designs, note that the MAX 7000 family is in legacy support - consider the MAX II or MAX V series for cost-sensitive modern designs, but the EPM7128 remains a proven solution for sustaining legacy 5V systems and as a pin-compatible firmware drop-in. This page synthesizes distributor pricing (as of 2026-09-13), drop-in pin-compatible alternatives (including the Atmel/Microchip ATF1508AS family noted by the Intel/Altera community as a silicon drop-in), practical design notes, and a parameter comparison matrix not found in the original datasheet alone.
EPM7128SQC100-7F - MAX 7000S 128-Macrocell CPLD 7.5ns | Altera
The Altera EPM7128SQC100-7F is a 128-macrocell CMOS CPLD from the MAX 7000S family, housed in a 100-pin PQFP (Plastic Quad Flat Pack) package. It delivers 7.5 ns pin-to-pin logic delay, 125 MHz maximum operating frequency, and 84 user I/O pins with 5V (4.75V–5.25V) tolerance, providing approximately 2,500 usable gates for glue-logic, bus-interface, and state-machine consolidation tasks. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable IC that implements combinational and sequential logic in a single chip. CPLDs sit hierarchically between simple PLDs and FPGAs: they offer predictable timing (fixed propagation delay), deterministic power-up behavior, and much higher logic density than 22V10-style GALs, but lower density than SRAM-based FPGAs. MAX 7000S belongs to the EEPROM-based CPLD class — the configuration is retained without external memory and the device is in-system programmable (ISP) via JTAG. Key features of the EPM7128SQC100-7F include eight logic array blocks (LABs) of 16 macrocells each, a programmable interconnect array (PIA), per-macrocell flip-flops with clear/preset, and JTAG boundary-scan test (BST) circuitry compliant with IEEE 1149.1. The 'SQC100' package code denotes a surface-mount PQFP-100 at commercial 0 °C to 70 °C temperature range, while the '-7F' speed suffix specifies the 7.5 ns tPD grade with lead-free (Pb-free) matte-tin terminations. The architecture uses 5V-tolerant I/O with multi-voltage support, open-drain output option, and a global clock network shared by all LABs. Each macrocell contains a product-term array of 5×32 = 160 gates feeding a programmable register, which can be bypassed for pure combinational logic. Compared to its MAX 7000E predecessor, the 'S' (suffix S) variant adds JTAG BST in 128-macrocell and larger devices, expanded ISP capability, and the open-drain output option for wired-OR/wired-AND buses. Typical applications include legacy peripheral bus decoding (ISA, PCI, VME glue logic), address/data multiplexing between microprocessors and memories, state-machine controllers in industrial automation, and board-level configuration management in telecom and networking line cards. The instant-on behavior makes it well suited for boot-time logic that must be valid before any processor begins execution. When designing with this part, note that the MAX 7000S series is mature and Intel/Altera has marked most OPNs as obsolete or last-time-buy; verify current lifecycle status before starting a new design. For new designs where lifecycle supply assurance matters, evaluate the MAX II or MAX V families as modern equivalents. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet, helping engineers source, replace, and integrate the EPM7128SQC100-7F reliably.
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
The Intel (formerly Altera) EPM7128SQC100-7N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, packaged in a 100-pin Plastic Quad Flat Pack (PQFP). The device integrates 128 macrocells, 8 logic array blocks, 2 global clocks, and up to 84 user I/Os, delivering 2,500 usable system gates with 5ns pin-to-pin delays and counter speeds up to 175.4 MHz in the -7 speed grade (7.5 ns tPD). A CPLD (Complex Programmable Logic Device) is a non-volatile reconfigurable logic device that bridges the gap between small PLDs and large FPGAs. It contains multiple PAL-like logic blocks interconnected by a programmable switch matrix, with non-volatile EEPROM storage that retains configuration without external memory. The MAX 7000 family sits in the CPLD -> Programmable Logic -> Logic IC -> Integrated Circuit taxonomy, traditionally used for glue logic, bus interfacing, and state-machine replacement. Key features include In-System Programmability (ISP) via IEEE 1149.1 JTAG, 32 product terms per macrocell, multiVolt I/O supporting 2.5V/3.3V/5V mixed-voltage interfacing, and individually programmable security bits. The device is fabricated on a 0.30µm CMOS EEPROM process, providing instant-on operation since configuration is stored on-chip. Typical applications span legacy industrial glue logic, address decoding and bus arbitration in microcontroller/microprocessor systems, peripheral I/O expansion, and state-machine implementation. Its 5V-tolerant I/O makes it especially useful for translating between 5V legacy buses and 3.3V modern logic. When designing with this part, note that the EPM7128SQC100-7N is now reported as Obsolete by Arrow, with the -N suffix denoting lead-free (Pb-free) packaging. Designers of new products should evaluate the ATF1508AS from Microchip as a silicon drop-in alternative.
EPM7128SQC160-10 - MAX 7000 CPLD, 128 Cells, 100 I/O, 10ns | Altera
The Altera (Intel) EPM7128SQC160-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, delivering 128 macro cells, 2,500 usable gates, and 100 user I/O pins in a 160-pin PQFP (Plastic Quad Flat Pack) package with 10ns pin-to-pin propagation delay. Operating from a 5V core supply (with 3.3V or 5V I/O compatibility), the device provides in-system programmability via the IEEE Std. 1149.1 JTAG interface plus a legacy Altera ByteBlaster parallel port, enabling rapid prototyping and field upgrades. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that integrates multiple PAL-like logic blocks (called macro cells) onto a single chip with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy below FPGAs but above discrete glue logic, offering deterministic timing, predictable routing delays, and the ability to replace many SSI/MSI logic packages with a single device. The MAX 7000 family is Altera's second-generation MAX architecture, optimized for high-speed bus bridging, state-machine decoding, and peripheral interface glue logic. Key features of the EPM7128SQC160-10 include 128 macro cells (each containing a programmable AND/OR array and a configurable flip-flop with clear, preset, and clock-enable controls), 8 dedicated logic array blocks (LABs), a global interconnect called the Programmable Interconnect Array (PIA), and a per-pin tri-state buffer with user-programmable slew-rate control. The device supports hot-socketing insertion, I/O pins are 5V-tolerant with PCI-compliant drive capability, and in-system programming duration is typically under one second via JTAG. The 10ns speed grade provides a maximum toggle frequency of 100 MHz, sufficient for memory interfaces, bus arbitration logic, and high-speed glue logic. Architecture-wise, the EPM7128SQC160-10 uses Altera's classic EEPROM-based configuration cells (one per macro-cell bit), which means the design is non-volatile and retains its programmed logic without external boot memory - true instant-on behavior. Designers typically use Quartus II (legacy) or the MAX+PLUS II classic toolchain for design entry, fitting, and JTAG programming. The Programmable Interconnect Array (PIA) routes any LAB output to any other LAB input with fixed delay, simplifying static timing closure. Typical applications include PCI bus interface bridging, memory address decoding and chip-select generation, microcontroller peripheral expansion (address/data bus de-multiplexing), legacy 8051/68k/ColdFire system glue logic, and industrial control boards replacing dozens of 74LS/74F-series logic packages. Industrial designers also use the part for state-machine controllers and bus arbitration between multiple masters. Compared to FPGAs, the EPM7128S offers sub-100 mW standby power and deterministic 10 ns logic-array delays without configuration time. Design consideration: the 160-pin PQFP has 0.65 mm lead pitch and requires careful PCB layout to avoid solder bridges - a reflow profile with proper soak and peak temperature stages is recommended. Designers should also note that Quartus II support for legacy MAX 7000 devices requires the legacy device-support installer add-on. This page synthesizes distributor pricing, drop-in MAX 7000 speed-grade alternatives, JTAG programming guidance, and practical design notes not found in the manufacturer datasheet alone.
EPM7128SQC160-10N - 128-Macrocell MAX 7000 CPLD, 100MHz | Intel
The Intel (formerly Altera) EPM7128SQC160-10N is a 128-macrocell Complex Programmable Logic Device (CPLD) from the MAX 7000 family, housed in a 160-pin PQFP (Plastic Quad Flat Pack) package. It operates at 5V with up to 100 MHz counter frequency and 10 ns pin-to-pin delays, providing 2,500 usable gates and 100 user I/O pins for high-density glue-logic designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-based programmable logic device that combines the deterministic timing of PAL/GAL architectures with higher logic density. It sits hierarchically below an FPGA but above simple PLDs in the programmable logic taxonomy: CPLD -> PLD -> programmable logic -> semiconductor. Compared to FPGAs, CPLDs offer instant-on configuration, predictable timing, and lower power for moderate-density glue logic. Key features include 128 macrocells (each with 36 product terms), 5V core supply, in-system programmability via JTAG (IEEE 1149.1), and built-in JTAG boundary-scan test circuitry on MAX 7000S devices with 128 or more macrocells. The 5-ns pin-to-pin logic delays and 175.4-MHz counter frequencies make the EPM7128SQC160-10N a strong fit for bus-interface bridging and address decoding in legacy 5V systems. The MAX 7000 architecture employs a second-generation MAX fabric with a global interconnect matrix, programmable interconnect array (PIA), and per-macrocell flip-flops. CMOS EEPROM technology stores configuration non-volatilely, so the device powers up in a known state with no external boot PROM, a defining advantage over SRAM-based FPGAs in deterministic boot applications. Typical applications include PCI/ISA bus interface logic, address decoding, glue logic for microprocessors, state-machine control, and 5V system prototyping. It is also used in industrial controllers, telecom backplane glue logic, and legacy system upgrades where 5V tolerance is mandatory. When designing, note that this part is in the MAX 7000 family and shares the classic Altera ByteBlaster/USB-Blaster programming flow via JTAG. Decoupling: place 0.1 uF and 10 uF caps near each supply pin pair to keep the global interconnect matrix quiet during simultaneous switching. This page synthesizes distributor pricing, same-family MAX 7000 drop-in alternatives (including speed-grade and temperature-grade variants), and practical design notes not found in the original manufacturer datasheet.
EPM7128SQC160-15 - MAX 7000 CPLD, 128 Macrocells, 100 I/O | Intel
The Intel (formerly Altera) EPM7128SQC160-15 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, offering 128 macrocells, 2,500 usable gates, and 100 user I/Os in a 160-pin PQFP package with a 15 ns pin-to-pin propagation delay. Built on Altera's second-generation MAX architecture, it combines non-volatile EEPROM configuration memory with a 5V-tolerant I/O ring, making it suitable for legacy 5V system designs and 3.3V-tolerant interfaces. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the digital logic hierarchy between simple PLDs (PALs/GALs) and FPGAs. CPLDs use a deterministic, AND-OR fabric with macrocell-based logic blocks and a global interconnect that guarantees predictable, fixed propagation delays independent of routing density. This deterministic timing makes CPLDs ideal for glue logic, bus decoding, address mapping, state-machine control, and high-speed control-plane tasks where every nanosecond of delay must be accounted for at synthesis time. Key differentiating features include a maximum operating frequency of 125 MHz (with internal feedback), 4.5 ns logic-element propagation delay, in-system programmability via IEEE 1149.1 JTAG, and support for 5V/3.3V multi-voltage I/O via the MAX 7000S I/O ring. The 160-pin PQFP (Plastic Quad Flat Pack) package provides a generous thermal envelope for industrial and commercial temperature grades. Power consumption is dominated by static I/O current and scales with toggle frequency, with a typical ICC of approximately 100-150 mA at full operation. Technically, the EPM7128SQC160-15 uses 8 logic array blocks (LABs) of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O feedback paths. The EEPROM configuration cell retains logic design without external memory, supports 100 erase/program cycles, and allows instant-on behavior at power-up. The JTAG interface supports both boundary-scan testing and in-system programming, enabling board-level test access and field upgrades. Typical applications include bus-interface glue logic for 5V and 3.3V microcontroller systems, address decoding and chip-select generation for memory and peripheral buses, peripheral control and state-machine implementation in industrial controllers, legacy system replacements for discrete 74-series logic, and high-speed control logic in test-and-measurement equipment. The deterministic timing model also makes the EPM7128SQC160-15 well-suited for protocol bridging between microcontrollers and older peripheral ASICs. When designing with the EPM7128SQC160-15, note that the part is now in obsolescence transition - many MAX 7000 devices are listed as obsolete at Intel/Altera. Engineers should verify last-time-buy status with the manufacturer and plan migration paths to MAX II or MAX V CPLDs (which are 3.3V/2.5V/1.8V-only and require re-synthesis). Existing designs with stable long-term supply should consider a second-source strategy, since EPM7128SQC160-15 was originally a single-source part. This page synthesizes distributor pricing, verified drop-in alternatives drawn from the MAX 7000 family, and practical design notes - information not consolidated in the original Altera datasheet. All specifications are cross-checked against the manufacturer datasheet and current distributor listings.
EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera
The Intel / Altera (formerly Altera) EPM7128SQC160-15N is a 128-macrocell, 100-IO Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000 family, housed in a 160-pin Plastic Quad Flat Pack (PQFP-160 / BQFP-160) package. Built on a 5V-tolerant CMOS EEPROM process, it provides 15ns pin-to-pin logic delay, a 76.9 MHz internal counter frequency, and 2.5K usable gates, making it suitable for medium-density glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with the density of a small FPGA. Within the broader programmable-logic taxonomy, CPLDs sit between discrete PALs (small, simple, fast) and FPGAs (large, register-rich, SRAM-based). The MAX 7000 family was Altera's second-generation CPLD architecture (succeeding the classic MAX 5000/9000) and introduced the multi-matrix interconnect plus ISP (in-system programmability) via JTAG, features that made it the de-facto industry standard for glue logic from the mid-1990s onward. Key features of the EPM7128SQC160-15N include 128 macrocells arranged in 8 logic array blocks (LABs), 100 user I/O pins, 15ns combinatorial propagation delay, a maximum internal counter frequency of 76.9 MHz, and 5V-tolerant I/O supporting both 3.3V and 5V mixed-voltage systems. The device is non-volatile (EEPROM-based) so the configuration is retained without an external boot PROM, and it supports in-system programming via the JTAG-compatible 4-pin interface. Programmable interconnect allows wide AND-OR logic functions across LABs with predictable timing. The architecture uses Altera's classic MAX (Multiple Array matriX) routing structure: each LAB contains 16 macrocells that share a programmable interconnect array, and LABs communicate through the PIA (Programmable Interconnect Array). This gives the EPM7128SQC160-15N deterministic, pin-locked timing that does not change with routing density - a property that distinguishes CPLDs from SRAM-based FPGAs where delay varies with placement. Typical applications include bus-interface bridging (PCI/ISA glue logic), address decoding and chip-select generation, power-up sequencing and reset distribution, motor control peripheral logic, industrial PLC I/O expansion, and replacement of multiple discrete TTL/CMOS logic packages. The wide 5V I/O tolerance is especially valued when interfacing legacy microcontrollers or bus transceivers to modern 3.3V ASICs. When designing with this device, note that the PQFP-160 footprint has longer lead lengths than modern BGA/QFN packages, which limits high-speed signal edge rates above ~50 MHz. For new designs above 100 MHz I/O, consider migrating to a MAX V, MAX 10, or MAX II CPLD in a smaller QFN package while preserving the MAX 7000 logic architecture. This page synthesizes distributor pricing, SameFrame-pinout drop-in alternatives, and practical glue-logic design notes not found in the original 1998-vintage datasheet.
EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
The Altera (Intel) EPM7128SQC160-6 is a 128-macrocell member of the MAX 7000S family of Complex Programmable Logic Devices (CPLDs) housed in a 160-pin Plastic Quad Flat Pack (PQFP) package. It is built on a 0.5 µm CMOS EEPROM process with 2.5K usable gates and offers a pin-to-pin propagation delay of 6 ns, making it suitable for high-speed glue-logic, bus decoding, and interface bridging applications. The device operates from a single 5 V supply (4.75 V – 5.25 V) and provides 100 user I/O pins organized in 4 I/O banks, supporting both 5 V and 3.3 V LVTTL/LVCMOS interfacing when configured via the Quartus or MAX+PLUS II toolchains. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell arrays with a central interconnect matrix. In the system hierarchy, the CPLD sits between simple SPLDs (PAL/GAL) and larger FPGAs, offering deterministic timing, low power, and in-system programmability via IEEE 1149.1 JTAG. MAX 7000S devices are particularly favored for glue logic, address decoding, peripheral bridging, and state-machine controllers where deterministic propagation delay is more important than raw gate count. Key features include in-system programmability through JTAG (IEEE Std 1149.1), 128 macrocells distributed across 4 logic array blocks (LABs), 2.5K equivalent gates of usable logic, 100 user I/O pins, and an internal fmax of 147.1 MHz. The EPM7128SQC160-6 supports ISP (In-System Programming) via the dedicated JTAG pins, allowing field upgrades without removing the device from the PCB. The architecture provides predictable interconnect delays and a global clear/preset network. The MAX 7000S architecture uses a classic EEPROM-based, non-volatile programming cell that retains configuration indefinitely without external memory. Each macrocell contains a programmable AND/OR array plus a configurable flip-flop, with product-term allocation steering logic to balance speed and density. The 6 ns speed grade is the second-fastest commercial bin in this family (only 5 ns is faster), making the -6 well suited for memory interface controllers, bus bridges, and high-speed state machines where the 10 ns and 15 ns grades are too slow. Typical applications include address decoding for 8/16/ and 32-bit microprocessors, asynchronous bus interfaces between processors and peripherals, peripheral controllers (UART, timers, interrupt controllers), I/O expansion, and 5 V glue logic on legacy industrial platforms. The PQFP-160 footprint allows drop-in replacement of the slower EPM7128SQC160-10 and EPM7128SQC160-15 grades with identical pinout. When designing with this part, note that the part is mature and approaching obsolescence - verify long-term supply before committing to new designs. For new designs, consider MAX II (EPM240) or MAX V CPLDs in modern packages for better toolchain support. Use Quartus II 13.0 or earlier, or MAX+PLUS II, for synthesis and fitting. This page synthesizes distributor pricing, drop-in alternatives drawn from the same MAX 7000S family, and practical design notes not consolidated on any single distributor page.
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
The Altera (Intel) EPM7128SQI100-10 is a member of the MAX 7000S family of high-density, high-performance CMOS Complex Programmable Logic Devices (CPLDs) based on Altera's second-generation MAX architecture. It provides 128 macrocells, 84 user I/Os, and 2,500 usable gates in a 100-pin PQFP package, with pin-to-pin propagation delay of 10 ns and a maximum internal frequency of 125 MHz to 250 MHz depending on configuration. The "I" suffix designates the industrial operating temperature range of -40C to +85C, while the "Q" denotes the PQFP-100 package option. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the architectural simplicity of a PAL with the density and flexibility of an FPGA. CPLDs sit in the programmable logic hierarchy between simple SPLDs (single PAL/GAL arrays) and FPGAs (gate-array style SRAM-based devices). They use EEPROM or flash configuration cells, retain their configuration without external memory, and are typically used for glue logic, bus bridging, state-machine control, and address decoding in cost-sensitive industrial designs. The MAX 7000S family targets 5V tolerant interfaces and provides in-system programmability (ISP) via IEEE 1149.1 JTAG. Key features of the EPM7128SQI100-10 include pin-to-pin delays of 10 ns, counter speeds up to 175.4 MHz, 100% TTL-compatible I/O, JTAG-compliant ISP, and an extended industrial temperature range. The device supports 5V core operation with multi-voltage I/O support, making it suitable as a bridge between legacy 5V logic and modern 3.3V peripherals. Built-in JTAG (IEEE 1149.1) boundary-scan support simplifies board-level test. Architecturally, the MAX 7000S device uses Logic Array Blocks (LABs) of 16 macrocells each, interconnected via a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR/registered logic block with configurable flip-flop polarity, clock, clear, and preset controls, and an I/O control block with tri-state, open-drain, or registered output options. The EEPROM cell technology guarantees 100 reprogram/erase cycles minimum. Typical applications include industrial control glue logic, bus interface bridging (e.g., PCI to local bus), address decoding and chip-select generation, state-machine controllers in motor drives, and 5V-to-3.3V level translation in legacy system upgrades. The 84 user I/Os make it well-suited for medium-density interface aggregation. When designing with the EPM7128SQI100-10, ensure the 5V VCC supply is well-decoupled with 0.1uF and 10uF capacitors placed close to the device. Unused I/O pins should be configured as outputs and left unconnected, or tied to a defined logic level through the Quartus design software. Industrial-grade parts require proper thermal management at high toggle rates. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes drawn from the MAX 7000S datasheet family, providing information not consolidated on any single distributor or manufacturer page.
EPM7128SQI100-10N - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-100 | Intel / Altera
The Intel / Altera EPM7128SQI100-10N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 128 macrocells, 84 user I/Os, 2,500 usable gates, and 10 ns pin-to-pin logic delays in a 100-pin PQFP (Plastic Quad Flat Pack) package. It operates from a 5 V core supply and supports programmable VCCIO for mixed 3.3 V / 5 V I/O interfacing, with counter frequencies up to 175.4 MHz and ISP (in-system programmability) via JTAG. What is a CPLD? A Complex Programmable Logic Device is a non-volatile, reprogrammable digital IC that sits between simple PAL/GAL spld devices and high-density FPGAs. CPLDs (hierarchy: CPLD -> PLD -> programmable logic -> digital IC -> semiconductor) use a deterministic routing fabric and on-chip EEPROM/flash configuration memory, so they retain logic at power-up with no external boot PROM. The MAX 7000S family from Altera (now Intel FPGA) is a second-generation MAX architecture family widely used as glue logic, bus bridges, and state-machine controllers in industrial, telecom, and embedded designs. Key features of the EPM7128SQI100-10N include 5-ns pin-to-pin delays (commercial speed grade), 100 MHz maximum operating frequency, IEEE Std. 1149.1 JTAG boundary-scan test (BST) circuitry, multiVolt I/O for 2.5 V / 3.3 V / 5 V interfacing, and individual macrocell clear/preset for synchronous or asynchronous control. The 'I' suffix indicates the industrial temperature grade (-40C to +85C), and the 'N' suffix indicates a lead-free / Pb-free RoHS-compliant assembly. Architecturally, the EPM7128SQI100-10N organizes its 128 macrocells into four Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array plus a configurable flip-flop with product-term clock, clear, and preset - giving designers 32 product terms per macrocell for sum-of-products logic. The deterministic PIA routing yields predictable, glitch-free timing that is independent of design placement - a key advantage over FPGAs for control-plane logic. Typical applications include bus decoding and address mapping, peripheral chip-select generation, state-machine controllers, I/O expansion and bus bridging, glue logic between microprocessors and peripherals, and JTAG-controlled test access. The wide I/O count and PQFP-100 footprint make it well-suited for legacy industrial backplanes and 5 V-tolerant designs. When designing with this device, ensure the VCCINT-to-VCCIO supply sequencing follows the datasheet monotonic-rise requirements and that unused I/O pins are correctly terminated (per AN 74). The JTAG chain should include the proper bypass instructions to avoid contention when multiple devices share TCK/TMS. This page synthesizes distributor pricing, drop-in compatible alternatives, and practical design notes that go beyond the manufacturer datasheet to help engineers select, source, and apply the EPM7128SQI100-10N with confidence.