FPGA & CPLD
Products (6,800+)
EPM5192LC-25 - MAX 5000 CPLD, 192 Macrocells, 25ns | Altera
The Altera EPM5192LC-25 is a high-density, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, delivering 192 macrocells with a 25 ns pin-to-pin logic delay in a ceramic J-leaded chip carrier (JLCC) package. It belongs to the classic Altera MAX CPLD lineage later absorbed into the Intel (formerly Altera) Programmable Solutions Group portfolio, and continues to serve installed bases in industrial, telecommunications, and military systems where long-life, mature CPLD silicon is preferred. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that contains multiple PAL-like macrocell arrays interconnected by a central programmable switch matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs (PALs/GALs) and below FPGAs, providing deterministic pin-to-pin timing, fast combinational logic, and instant-on behavior - making them ideal for glue logic, bus interfacing, and state-machine decoding. The EPM5192LC-25 is a member of the high-density MAX 5000 sub-family, which scales up the classic MAX architecture to 192 macrocells and large I/O counts. Key features include 192 logic macrocells, a 25 ns worst-case pin-to-pin propagation delay (tPD), high-speed I/O with TTL-compatible thresholds, and built-in JTAG-based in-system programming via the MAX+PLUS II toolchain (legacy Altera software). The device is non-volatile, retaining its configuration without external memory, and the LC suffix indicates a ceramic JLCC package rated for commercial temperature operation with UV-erasable window capability for development and re-programming cycles. Architecturally, the EPM5192LC-25 employs Altera's classic MAX Logic Element Array (LEA) fabric with a global programmable interconnect, dedicated input registers, and I/O control blocks that support configurable slew rates and pull-ups. The 25 ns speed grade reflects the worst-case commercial-spec timing over the full operating range, sufficient for many bus-interface and decoder applications in the 30-40 MHz logic-rate envelope. Typical applications include legacy bus-interface glue logic (ISA, VME, PCI bridges), address decoding and chip-select generation, state-machine controllers for industrial control, peripheral I/O expansion, and migration targets for obsolete bipolar PAL devices. The UV-erasable window makes it suitable for prototyping, while OTP-mode production units are used for deployed systems. When designing with this device, confirm that the 25 ns tPD satisfies the setup-time budget of the downstream logic. For new designs, modern MAX II/MAX V CPLDs are recommended; the EPM5192LC-25 is primarily sourced for legacy maintenance, repair, and military programs requiring the original MAX 5000 silicon. This page synthesizes distributor availability, same-brand Altera drop-in alternatives, and practical design notes not found in the original 1990s datasheet - giving engineers a one-stop reference for legacy MAX 5000 maintenance.
EPM5192LC-2N - 192-Macrocell MAX 5000 EPLD, LC-2 Speed | Altera
The Altera EPM5192LC-2N is a 192-macrocell, UV-erasable high-density EPLD from the MAX 5000 family, supplied in a ceramic (LC) package and rated at the LC-2 commercial speed grade. Built on Altera's second-generation MAX architecture, the device integrates 192 macrocells with up to 192 flip-flops and 192 dedicated logic inputs, plus a global interconnect that lets any macrocell drive any I/O pin or feedback path. The -2N suffix denotes the commercial -2 speed bin (tPD approximately 25 ns) and a lead-free, RoHS-compliant termination finish. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that uses EPROM/EEPROM/flash cells to store the AND-OR logic pattern. EPLDs sit in the programmable-logic hierarchy below modern CPLDs and FPGAs, offering fast pin-to-pin combinational delay, deterministic timing, and simple JTAG/ISP programming. They are used for glue logic, address decoding, bus interfacing, state-machine implementation, and counter/timer functions in legacy designs. The MAX 5000 family is the classic Altera high-density EPLD line, predating the MAX 7000/MAX II CPLD families. Key features include 192 logic macrocells, 192 flip-flops, programmable I/O architecture with up to 96 I/O pins (package-dependent), and a typical combinatorial propagation delay of 25 ns at the -2 speed grade. The device supports 5V tolerant inputs on legacy LC nodes, in-system programmability via Altera's programming hardware, and JTAG boundary-scan test per IEEE 1149.1. Power consumption is typical for the MAX 5000 family at 5V VCC. The EPM5192LC-2N uses Altera's classic MAX architecture: a global Programmable Interconnect Array (PIA) that routes any macrocell output to any other macrocell input, giving a flat, predictable timing model. Each macrocell contains an AND-OR array feeding a configurable flip-flop, with programmable output polarity, clock, and feedback paths. Typical applications include legacy industrial control systems, telecommunication backplane glue logic, address decoding and wait-state generation in 80C186/68k/8051 microprocessor designs, bus arbitration, peripheral interfacing, and replacement/maintenance of older Altera MAX designs. The part is also widely used as a retrofit upgrade for older UV-erasable PAL/GAL-based boards. When designing with this part, ensure your target toolchain supports the legacy MAX 5000 device family (Altera MAX+PLUS II or compatible). Verify the speed grade is sufficient for the timing budget - the -2 (25 ns tPD) grade suits many asynchronous decoding and glue-logic paths but is too slow for high-speed synchronous buses. This page synthesizes parametric specifications, drop-in alternatives within the MAX 5000 family, current distributor stock, and practical design notes not consolidated in any single datasheet.
EPM5192LC-35 - MAX 5000 CPLD, 192 Macrocells, 35ns | Altera
The Altera EPM5192LC-35 is a high-density, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, delivering 192 macrocells with a 35ns pin-to-pin propagation delay in a ceramic J-leaded chip carrier package. Built on Altera's classic MAX architecture, it integrates multiple PAL-like logic array blocks (LABs) with a global programmable interconnect array, providing a non-volatile, deterministic logic replacement for dozens of discrete 74-series TTL devices. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays with a centralized interconnect matrix, sitting in the hierarchy between simple SPLDs and higher-density FPGAs. CPLDs offer deterministic timing (predictable pin-to-pin delays regardless of routing), instant-on behavior (no configuration boot), and high-drive I/O, making them well suited for glue logic, bus interfacing, address decoding, and control-state machines. The EPM5192LC-35 belongs to the MAX 5000 generation, which preceded the MAX 7000/MAX II families and is now considered legacy but still found in long-lifecycle industrial, military, and aerospace systems. Key features of the EPM5192LC-35 include 192 macrocells (organized across multiple LABs), 35ns worst-case tPD through the interconnect, and Altera's classic I/O structure supporting TTL-compatible levels. The device is in-system programmable via Altera's legacy programming hardware, with the "LC" suffix indicating a ceramic J-leaded chip carrier (JLCC) package and "-35" denoting the 35ns speed grade. As a member of the MAX 5000 family, it shares the same Altera programming algorithm as the broader family, simplifying firmware tooling. Architecturally, the MAX 5000 family uses an EEPROM/EPROM-based macrocell array paired with a continuous programmable interconnect array (PIA). This delivers predictable combinational and registered logic with deterministic 35ns delays, which is critical for asynchronous bus decoding and protocol-bridging applications where FPGAs introduce unpredictable timing. The LC package offers hermetic sealing for harsh-environment deployment. Typical applications for the EPM5192LC-35 include industrial control glue logic, legacy bus interface adapters (ISA, VME, and similar parallel buses), address decoding for microprocessor systems, military/aerospace avionics where the ceramic LC package meets hermeticity requirements, and replacement of multiple discrete 74LS/74F TTL packages with a single programmable part. The UV-erasable windowed package is also useful during prototyping and design iteration. When designing with this device, note that the 35ns tPD is the worst-case across all paths and corners - actual propagation is typically faster. Engineers migrating from this part should consider modern pin-compatible alternatives such as MAX 7000 series devices in PLCC packages, which offer faster speeds, lower power, and broader tool support while preserving the same logic footprint. This page synthesizes distributor availability, parametric drop-in alternatives from the Site MPN list, and practical design guidance for legacy MAX 5000 designs - information not collected in a single place in the original Altera datasheet.
EPM5192LC-45 - MAX 5000 CPLD 192 Macrocells | Altera
The Altera EPM5192LC-45 is a member of the classic MAX 5000 family of high-density, high-speed UV-erasable/OTP Complex Programmable Logic Devices (CPLDs), delivering 192 macrocells in a ceramic-windowed LCC package with a 45 ns pin-to-pin delay. It is manufactured by Altera (now part of Intel PSG) and belongs to the EPM5192 die family, which combines EPROM-based configuration memory with a programmable AND/OR logic array for glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and large FPGAs in the programmable logic hierarchy: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. CPLDs typically offer predictable timing, instant-on behavior, deterministic I/O placement, and lower power consumption than SRAM-based FPGAs, making them ideal for decoder, multiplexer, state-machine, and bus-arbitration roles where deterministic propagation delay matters more than raw gate density. Key features of the EPM5192LC-45 include 192 macrocells, 48 dedicated input pins, a maximum toggle frequency of 100 MHz, and a 45 ns tPD (pin-to-pin delay) over commercial 0C to +70C operating range. The part uses Altera's classic MAX architecture with a programmable interconnect array (PIA) and supports the company's MAX+PLUS II and older AHDL toolchains. The 'LC' suffix indicates a ceramic-windowed LCC package suitable for prototype and UV-erase development cycles. The EPM5192LC-45 sits in the hierarchy: programmable logic -> CPLD -> MAX 5000 family -> EPM5192 die. It targets older designs, legacy industrial controllers, and educational applications where the developer needs in-system UV erasure and re-programming, or where the design must remain bit-stream-compatible with vintage AHDL/MAX+PLUS II code bases. Typical applications include bus interface glue logic, address decoding, state-machine controllers, and legacy industrial automation retrofits. The 'LC-45' speed grade (-45 = 45 ns tPD) places it in the medium-speed tier of the EPM5192 family and is appropriate for asynchronous logic, address decoding, and slow peripheral interfaces. When designing with this part, note that the EPM5192 family has been discontinued by Intel PSG and is generally only available through obsolete-stock distributors. New designs should target MAX II, MAX V, or MAX 10 CPLD families. The ceramic LCC window package requires a UV eraser for reprogramming. This page synthesizes distributor pricing, same-brand drop-in alternatives from the EPM5192 family, and practical sourcing notes not found in the original datasheet.
EPM5192LC-M089A - 192-Macrocell MAX 5000 CPLD | Altera
The Altera EPM5192LC-M089A is a 192-macrocell CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, organized as 7 dedicated inputs and 64 I/O lines with a propagation delay of 55 ns in a 5V tolerant architecture. It is one of the high-density members of the MAX 5000 series and is supplied in a windowed ceramic or plastic package variant per the -M089A ordering code, supporting both UV-erasable and one-time-programmable (OTP) configuration flows for prototype through production use. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that sits between simple SPLDs/gal-style PLDs and high-density FPGAs in the programmable logic hierarchy. Internally, a CPLD is built from multiple logic array blocks (LABs) connected by a programmable interconnect array (PIA), giving deterministic timing that engineers rely on for glue-logic, bus decoding, and state-machine tasks. The MAX 5000 family specifically targets 5V systems and pin-compatible upgrades of legacy 22V10-class designs with higher macrocell counts. The taxonomy is: programmable logic device -> CPLD -> MAX 5000 -> 5V high-density CPLD. Key features of the EPM5192LC-M089A include 192 macrocells, 12 LABs interconnected through a Programmable Interconnect Array, a single global clock input, and 5V CMOS process technology. The architecture is described in the manufacturer datasheet as High-Speed, High-Density MAX 5000 Devices, optimized for high-speed combinatorial and registered logic with predictable timing. The 'LC' speed grade denotes 55 ns pin-to-pin propagation delay (tPD), and 'M089A' denotes the package/quality designation for the -M line. The EPM5192LC-M089A's non-volatile configuration, deterministic timing, and 5V I/O make it well suited for legacy industrial control boards, telecommunications interface logic, and military/aerospace applications that require erasable or one-time programmable parts. The Altera MAX 5000 series was originally introduced as a UV-erasable high-density CPLD family, and many of the -M variants are screened for extended-temperature or military-grade operation, which is why modern distributors still list EPM5192LC-M089A as a supported part for long-lifecycle programs. Typical applications include bus decoding and address mapping on VME/PCI/ISA backplanes, state-machine controllers for industrial automation, glue logic between microprocessors and peripherals, and replacement of multiple discrete 74LS/74F TTL packages in legacy systems. Designers choose this part when they need non-volatile, deterministic, 5V-tolerant logic in a high-macrocell count device. When designing with the EPM5192LC-M089A, observe the 5V VCC requirement and confirm that downstream devices tolerate 5V CMOS levels. Use the Altera MAX+PLUS II development toolchain for design entry, fitting, and programming; modern Altera/Intel Quartus flows support many MAX 5000 legacy projects through device-translation files. Always derate propagation delay for temperature and supply variation per the manufacturer datasheet. This page synthesizes distributor pricing, parametric specifications from the manufacturer datasheet, drop-in alternative recommendations drawn from the same MAX 5000 family, and practical design notes that go beyond the bare datasheet summary.
EPM5192LC-M091A - MAX 5000 EPLD, 192 Macrocells, 5V CMOS
The Altera EPM5192LC-M091A is a 5V high-density CMOS Erasable Programmable Logic Device (EPLD) from the legacy Altera MAX 5000 family, organized as 192 macrocells with 7 dedicated inputs and 64 I/O lines. It is built around 12 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), supports one global clock input, and is fabricated in UV-erasable CMOS technology with propagation delay typically around 55 ns. The part is supplied in a low-profile ceramic/military-style package variant denoted by the "LC" pin-grid suffix, with the "M091A" customer-specific designator describing a specific die revision or test pattern. The MAX 5000 architecture is electrically and architecturally distinct from the later MAX 7000/MAX II/MAX V series, so modern Altera/Intel (Quartus-supported) MAX V CPLDs are NOT drop-in alternatives. A Complex PLD (CPLD), often called an EPLD in older datasheets, is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single die, allowing the integration of glue logic, state machines, address decoding, and bus interface logic that previously required multiple discrete 22V10/16V8 GAL/PAL devices. In the system hierarchy, CPLDs sit between discrete programmable logic arrays (PAL/GAL) and larger SRAM-based FPGAs: they provide predictable timing, instant-on behavior, and unlimited read cycles without external boot memory. The MAX 5000 family specifically targets 5V systems where modern 3.3V-only CPLDs cannot be used. The EPM5192LC-M091A delivers 192 macrocells - the largest in the MAX 5000 family - enabling integration of large state machines, peripheral controllers, and complex decode logic on a single device. Key features include 64 user I/O pins for bus-intensive designs, 7 dedicated inputs for high-fan-in clock and control signals, programmable macrocell flip-flops with selectable D/T/JK/SR modes, and a PIA routing fabric with deterministic interconnect delays. The device supports both combinatorial and registered logic with each macrocell providing product-term allocation and a programmable output polarity. Architecturally it uses EPROM/EEPROM cells for configuration retention, providing instant-on operation without external configuration memory. Typical applications include legacy industrial control boards, military and aerospace systems (the LC and 883 suffixes indicate MIL-STD-883 screening), 5V-only bus interface logic, address decoding for 8/16/32-bit microprocessors, and replacement of multiple discrete PAL/GAL devices in glue-logic consolidation. The MAX 5000 family is widely found in VMEbus, MIL-STD-1553, and older telecom backplane designs. When designing with this EPLD, note that the LC package denotes a specific pinout/customer designation rather than a generic JEDEC outline, so PCB footprints must be verified against the M091A mechanical drawing before layout. Designers should also confirm logic utilization with Altera's legacy MAX+PLUS II development toolchain since modern Quartus Prime does not support MAX 5000 devices. This page synthesizes verified distributor intelligence, parametric compatibility notes, and practical design considerations specific to the legacy MAX 5000 family not found in the original manufacturer datasheet.
EPM5192LC-M148A - Altera MAX 5000 EPLD 192-Macrocell | Altera
The Altera EPM5192LC-M148A is a UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, delivering 192 macrocells and up to 148 user I/O pins in a 148-pin package. It is a high-speed, high-density programmable logic IC intended for glue logic, bus interfacing, and state-machine replacement on industrial and telecom boards. The part belongs to Altera's mature MAX 5000 series, which was a widely-deployed generation of UV-erasable CMOS EPLDs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single die with a central interconnect matrix. CPLDs are typically used as deterministic, low-latency glue logic: power-up ready, predictable timing, and pin-for-pin replaceable with discrete 74-series logic. In the device taxonomy, EPM5192 sits above a standard PAL and below modern FPGAs, and MAX 5000 specifically was Altera's bridge family between PALs and the later MAX 7000 / MAX II series. The 'LC' suffix denotes a low-power CMOS process variant and the 'M148A' package code designates the 148-pin package used for the LC speed grade. Key features include 192 macrocells organized across multiple logic array blocks, 148 user I/O pins, 5-V tolerant I/O, and propagation delays measured in tens of nanoseconds, which is well-suited to bus and control-plane logic. The device is in-system programmable via Altera's classic MAX+PLUS II / Quartus toolchains, with JTAG support depending on the exact die revision. The 148-pin package gives designers significant pin resources for wide bus bridges and parallel state machines. Architecturally, MAX 5000 uses a global interconnect with predictable tPD/tCO timing, making it easier to constrain than SRAM-based FPGAs. Typical applications include industrial control logic replacement, legacy telecom backplane glue logic, address decoding for 8/16/32-bit microprocessor boards, peripheral bus interfaces, and power-up configuration sequencing for ASIC/FPGA systems. The wide I/O count and 5-V tolerance make it especially useful as a bridge between 5-V legacy peripherals and modern 3.3-V controllers. When designing with this part, confirm the package code against the 148-pin PCB footprint before laying out a board; the LC speed grade denotes specific tPD numbers per Altera's MAX 5000 datasheet. Because the part is a mature, legacy device, current lead times and stock vary significantly and may require sourcing through brokers. Engineers should validate revision against the original Altera datasheet and check for any last-time-buy notices before committing to new production. This page synthesizes distributor pricing, drop-in alternatives from the MAX 5000 family, and practical design notes not found in the manufacturer datasheet alone.
EPM5192LC-M205A - 192-Macrocell MAX 5000 CPLD | Altera
The Altera EPM5192LC-M205A is a 192-macrocell CMOS Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, offering 7 dedicated inputs, 64 I/O lines, and 55 ns propagation delay at 5V core supply in a 205-pin package. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell blocks interconnected by a programmable interconnect array (PIA). CPLDs sit between simple SPLDs and larger FPGAs in the programmable logic hierarchy: SPLD -> CPLD -> FPGA -> SoC. They are valued for deterministic timing, low power, and BOM-level glue-logic integration. Key features of the EPM5192LC-M205A include 192 macrocells organized into 12 Logic Array Blocks (LABs), a 55 ns pin-to-pin propagation delay (tPD), and a 5V VCC supply with UV-erasable / one-time-programmable (OTP) configuration memory. The shared input/clock architecture routes one global clock plus seven dedicated inputs to all LABs, and the PIA provides uniform interconnect delays that simplify static-timing closure. Architecturally, the device implements Altera's classic MAX 5000 EEPROM-based macrocell: each macrocell contains a programmable AND/OR array, a flip-flop, and an output enable, fed by 36 product terms. The CMOS EPROM technology yields zero standby current once programmed, and the 205-pin package provides ample I/O for bus- and control-plane integration. Typical applications include legacy industrial control glue logic, address decoding in 5V VME/PCI systems, bus-interface bridging, and state-machine replacement in long-lifecycle aerospace/defense platforms. The 5V tolerance and OTP memory make it well suited to designs that cannot tolerate SRAM-FPGA configuration time. When designing with this device, ensure the 5V supply is well decoupled and that the JTAG/ISP programming interface is brought out to a header. Because OTP variants cannot be re-programmed, keep one socketed unit for prototyping revisions. This page synthesizes distributor pricing, same-package alternatives, and practical design notes not found in the original Altera MAX 5000 datasheet, helping engineers assess migration paths.
EPM5192LC1 - 192-Macrocell MAX 5000 CPLD, 5V, PQCC-84 | Altera
The Altera EPM5192LC1 is a 192-macrocell, 64-I/O, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in an 84-terminal Plastic Leaded Chip Carrier (PQCC84 / JEDEC S-PQCC-J84) package. The device is built on a 5V CMOS process and operates from a nominal 5V supply with a permitted range of 4.75 V to 5.25 V. The EPM5192LC1 integrates 192 macrocells, 7 dedicated inputs, and 64 I/O pins, and is characterized for a maximum clock frequency of 50 MHz and a pin-to-pin propagation delay (tPD) of 40 ns. The die offers 3.75K equivalent gates of logic capacity. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic IC that sits between discrete logic (PAL/GAL) and FPGAs in the programmable logic taxonomy. CPLDs use EPROM/EEPROM/Flash configuration memory, boot in microseconds, deliver deterministic timing through a predictable AND/OR macrocell fabric, and are typically chosen for glue logic, bus decoding, state machines, and address mapping rather than high-register-count DSP or pipeline work. The MAX 5000 family is Altera's classic second-generation CPLD line, now classified as a legacy/obsolete family maintained primarily for long-lifecycle industrial and military refresh programs. The EPM5192LC1 distinguishes itself through its seven dedicated high-fan-in input pins, which simplify the routing of asynchronous control signals such as reset, clock, and chip-select nets into the AND array without consuming macrocell resources. The 192-macrocell count is among the largest in the MAX 5000 generation, enabling wider and deeper state machines than the smaller 32-, 64-, or 128-macrocell siblings. Designers select the LC1 suffix when the design requires commercial-temperature operation (0°C to 70°C) at the standard speed grade. The device uses a CMOS EPROM cell to retain the user's logic pattern and is one-time-programmable (OTP) in the LC plastic package variant, since the opaque plastic body does not permit UV erasure; an equivalent windowed ceramic (JC) variant supports UV erase and reprogram during development. Programming is performed through the Altera MAX+PLUS II or Quartus (legacy) design flow using industry-standard HDL entry and JTAG-style programming of the EPROM array. Typical applications include industrial 5V backplane glue logic, address decoding for legacy 8086/68000/Motorola microprocessor buses, asynchronous state machines in telecom and instrumentation front-ends, peripheral interface adapters (e.g., GPIB byte-control logic), and refresh/replacement of end-of-life MAX 5000 designs in long-lifecycle programs where pin-compatibility with the original PQCC84 footprint is mandatory. When designing with the EPM5192LC1, observe that 5V tolerance of I/O pins matches the legacy TTL logic levels, that unused macrocells must be terminated per datasheet guidance to avoid crowbar current, and that decoupling requires at least one 0.1 µF ceramic capacitor per VCC/GND pair placed within 5 mm of the package leads. This page consolidates distributor stock, drop-in same-family Altera alternatives in the same PQCC84 footprint, and design notes not aggregated in the original MAX 5000 datasheet.
EPM5192LC2 - 192-Macrocell MAX 5000 EPLD, PQCC-84 | Intel / Altera
The Intel / Altera EPM5192LC2 is a high-speed, high-density EPLD from the legacy MAX 5000 family, delivering 192 macrocells and 64 user I/O lines in an 84-pin PQCC (J-lead ceramic chip carrier) package. Built on a 5V CMOS process, this erasable programmable logic device offers a typical propagation delay of 45 ns (LC-2 speed grade) and supports a maximum clock frequency up to 50 MHz, making it suitable for glue-logic and state-machine integration in legacy industrial systems. The architecture is organized as 12 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), with 7 dedicated inputs (including one external clock input) for synchronous design entry. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines the non-volatility of EPROM storage with combinational and sequential logic resources. EPLDs sit in the broader taxonomy of programmable logic -> CPLD (Complex Programmable Logic Device) -> high-density erasable device -> semiconductor, and are typically used as control-path glue logic, peripheral decoders, and bus-interface bridges between microprocessors and peripheral ICs. Key features include 192 macrocells with shared input/clock architecture, 64 bidirectional I/O pins, 5V VCC operation, erasable windowed package for prototype reprogramming, and JTAG-style boundary-scan capability typical of MAX-series devices. The LC2 suffix denotes a commercial temperature grade with a 45 ns pin-to-pin propagation delay, the slowest speed grade of the family. Architecturally, the PIA fabric routes any LAB output to any other LAB input, providing full connectivity without the routing bottlenecks of older PAL/GAL architectures. Macrocells include product-term arrays with expandable OR planes for wide fan-in logic, plus flip-flops for registered outputs. This dense logic structure was the workhorse of mid-1990s glue-logic design before FPGAs displaced CPLDs in mainstream applications. Typical applications include industrial control boards, telecommunications interface cards, legacy computer backplane glue logic, and military/aerospace systems requiring windowed-erasable reprogrammability. Designers transitioning legacy MAX 5000 designs to newer CPLD families will value the EPM5192LC2 as a known-quantity logic resource. Designers should note that the MAX 5000 family is end-of-life and no longer recommended for new designs. Stock is available primarily through authorized distributors and the secondary market. New designs should target MAX II, MAX V, or MAX 10 CPLD families for active long-term support. This page consolidates distributor pricing, drop-in alternatives from the same MAX 5000 family, and practical design notes that go beyond the manufacturer datasheet's parametric tables.
EPM5192LC84 - 192-Cell OTP PLD, 55ns, LCC-84 | Altera / Cypress
The Altera (now Intel/Altera, also resold as Cypress) EPM5192LC84 is a high-density, UV-1, OTP (One-Time Programmable) CMOS Complex Programmable Logic Device (CPLD) from the classic MAX 5000 family, packaged in an 84-pin LCC (PQCC84 / MS-018) ceramic-compatible plastic carrier. According to distributor and datasheet summaries, it integrates 192 logic macrocells, supports propagation delays around 55 ns, and is built on a CMOS process designed for high-speed glue-logic, bus decoding, and state-machine integration. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the architecture of a PAL/GAL with on-chip EEPROM/EPROM/flash configuration memory. It sits in the programmable-logic hierarchy between simple SPLDs (PAL/GAL) and FPGAs. CPLDs offer deterministic timing, instant-on configuration, and high drive strength, making them ideal for bus interfacing, address decoding, and control logic. The MAX 5000 family is one of the earliest Altera CPLD generations, predating the MAX 7000/MAX II/MAX V lines, and is now classified as mature/last-time-buy across most channels. Key features of the EPM5192LC84 include 192 macrocells, 55 ns pin-to-pin propagation delay (tPD), CMOS low-power operation, and a generous 84-pin LCC footprint that exposes all user I/O for full utilization. The device is JTAG-configurable via Altera legacy programming tools (MAX+PLUS II baseline), supports multiple I/O standards of its era, and provides programmable macrocell flip-flops with separate set/reset and clock options. Technically, the MAX 5000 architecture uses a classic AND-OR programmable array feeding a flexible macrocell register. The 192-cell count equates to roughly 48 logic array blocks (LABs) in the MAX 5000 taxonomy. The 84-pin LCC package delivers robust thermal and mechanical performance for industrial and legacy military/avionics sockets. Because the device is OTP (or one-time-UV-erasable depending on variant), firmware is committed during manufacture or via windowed UV erasure in development. Typical applications include address/control bus decoding in 8086/68000-era microprocessor systems, glue logic replacement of multiple 74LS/74F TTL packages, industrial machine control boards, and legacy telecom backplane interfacing. The instant-on nature of the non-volatile configuration makes it well-suited to deterministic boot sequences where FPGAs would otherwise require external PROMs. When designing with this part, verify the programming algorithm in MAX+PLUS II legacy mode and confirm second-source availability through Altera/Intel distribution. The LCC-84 socket footprint requires through-hole or socketed mounting; PCB land pattern should match JEDEC MS-018 PQCC84. For new designs, evaluate MAX V (5M240Z) or MAX II (EPM240) as modern, in-production equivalents with similar macrocell counts and lower power.
EPM5192LC84-1 - 192-Macrocell MAX 5000 EPLD, UV-OTP | Altera
The Intel / Altera EPM5192LC84-1 is a 192-macrocell UV-erasable / one-time-programmable Complex Programmable Logic Device (EPLD) from the MAX 5000 family, supplied in an 84-pin PLCC package. It combines high density with high-speed CMOS EEPROM-based logic and is intended for glue-logic, bus-interface, and state-machine replacement in legacy industrial designs. A Complex PLD (CPLD/EPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a programmable interconnect matrix, providing greater logic capacity than classic 22V10-style SPLDs while preserving deterministic timing. Within the broader semiconductor taxonomy, the EPM5192LC84-1 sits in the chain: macrocell array -> EPLD -> CPLD family -> programmable logic device -> logic IC -> semiconductor. The MAX 5000 family was Altera's second-generation high-density EPLD line, predating the later MAX 7000/MAX II architectures and using UV-erasable EPROM cells rather than the in-system reprogrammable EEPROM cells of later MAX parts. Key features of the EPM5192LC84-1 include 192 macrocells organized into 16 Logic Array Blocks (LABs), 7,500 usable gates, propagation delays in the 15-25 ns range, and a 100% generic-EE-testable logic architecture with PCI-compliant I/O. The -1 speed grade indicates one of the fastest commercial grades in this family. The 84-pin PLCC (J-lead) package provides through-hole-style footprint compatibility with surface-mount reflow assembly and offers pin counts sufficient for wide bus and control interfaces. Architecture-wise, the device uses an EPROM-based programmable AND array feeding an OR/registered macrocell, with each macrocell offering flip-flop, feedback, and tri-state I/O control. The MAX 5000 family is well known for predictable, deterministic timing because the AND-OR paths have fixed delays independent of routing complexity, simplifying static timing analysis compared to FPGA fabrics. Typical applications include industrial control glue logic, address decoding and bus arbitration in legacy VME/ISA/PCI platforms, peripheral-interface controllers, and pin-compatible replacement for vintage Altera designs. Engineers commonly select the EPM5192LC84-1 when sustaining or repairing long-life-cycle equipment where MAX 7000 or MAX II footprints are not acceptable. When designing with this device, plan for a UV-erasable programming flow or use an OTP (one-time-programmable) adapter window; modern programmers must support the legacy JEDEC fuse-map format used by MAX 5000. Ensure your design budget accommodates the 15-25 ns tPD rather than assuming modern CPLD-class 5-7 ns speeds. This page synthesizes distributor pricing, same-brand MAX 5000 alternatives, and practical legacy-design notes not consolidated in the original Altera datasheet family brochure.
EPM5192LC84-2 - MAX 5000 CPLD 192 Macrocells 84-PLCC | Altera
The Altera EPM5192LC84-2 is a member of the classic MAX 5000 family of high-speed, high-density CMOS EPLDs (Erasable Programmable Logic Devices) housed in an 84-pin PLCC package. It provides 192 macrocells and is specified for commercial temperature operation with the speed grade suffix "-2", which denotes Altera's second-tier propagation delay rating for this die. The device is targeted at glue-logic, bus-interface, and state-machine consolidation applications that previously required multiple TTL/CMOS packages. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-rewritable digital IC that integrates AND/OR array logic, macrocell registers, and a programmable interconnect network onto a single die. The MAX 5000 family sits in Altera's taxonomy as a second-generation EPLD, sitting above simple PAL/GAL devices and below modern MAX II / MAX V non-volatile CPLDs. CPLDs offer deterministic propagation delay (independent of logic path), which makes them ideal for asynchronous interface bridging and bus decode logic where FPGAs' variable delay would be problematic. Key features of the EPM5192LC84-2 include 192 macrocells, a tPD (pin-to-pin propagation delay) defined by the speed grade suffix, programmable output polarity, and a JTAG-compatible or vendor-specific programming interface. The 84-pin PLCC (Plastic Leaded Chip Carrier) package is JEDEC-standardized and supports manual prototyping as well as volume surface-mount assembly. The device operates from a single 5V supply and consumes zero standby current when configured but unclocked. The EPM5192LC84-2 is built on a UV-erasable CMOS process (Altera denoted the OTP variant without the window as LC, while JEDEC ceramic-windowed versions were offered for development). The architecture combines a programmable AND array feeding a fixed OR array with each macrocell containing a flip-flop, output enable, and programmable polarity. Programming is performed via Altera's legacy programming hardware using a JEDEC-standard bitstream. Typical applications include 5V TTL glue logic replacement, microprogram sequencers, state-machine controllers, bus-address decoding, and legacy system upgrades where modern FPGAs would over-engineer the solution. Because the MAX 5000 family is from the early-1990s product generation, it is most commonly found in long-lifecycle industrial, military, and test-equipment designs that have been qualified for decades. Designers should note that the MAX 5000 family lacks modern features such as in-system programmability, hot-socketing, or 3.3V I/O tolerance - it is strictly a 5V TTL-compatible device. The "-2" speed grade is the slowest commercial tier; for higher speed, designers should consult the EPM5192GM/883B (military) variants or move to a MAX 7000/MAX 3000 family device. This page synthesizes XAIPART availability, parametric proximity to same-family variants, and practical design notes that are not duplicated in the original Altera datasheet or third-party distributor listings.
EPM5192LI - 192-Macrocell MAX 5000 CPLD 40MHz 5V | Altera
The Altera EPM5192LI is a high-density UV-erasable / OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, integrating 192 macrocells and approximately 3,750 usable gates in a CMOS architecture. It operates from a single 4.5V to 5.5V supply, supports a maximum toggle frequency of 40 MHz, and is housed in an 84-pin Plastic Leaded Chip Carrier (PQCC, package code J84) for surface-mount assembly. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays with a central interconnect matrix, providing deterministic timing, low power, and instant-on behavior. CPLDs sit in the programmable-logic hierarchy between small SPLDs (PAL/GAL) and large FPGAs, and are typically used for glue logic, bus decoding, address mapping, and control-state machines where predictable propagation delay is critical. Key features of the EPM5192LI include 192 macrocells organized into 12 interconnected Logic Array Blocks (LABs), 7 dedicated inputs, 72 total inputs, and 64 user I/O lines. The device offers a propagation delay of 55 ns and is built on a CMOS process with EPROM (UV-erasable) non-volatile elements, allowing repeated programming during development. The 'I' suffix denotes the industrial operating-temperature range. Architecturally, the MAX 5000 series uses a programmable AND/OR array with a global interconnect that ties each LAB to the device pins. This produces fixed pin-to-pin timing regardless of how the logic is fitted - a defining advantage over SRAM-based FPGAs for timing-critical control paths. The EPROM cells retain configuration indefinitely with the package window covered, eliminating the need for a separate boot memory. Typical applications include legacy industrial controllers, telecom interface glue logic, military/aerospace systems (in the JM/883 screened variant), and replacement designs for obsolete board-level decode logic. The 84-pin PQCC package offers a JEDEC-standard land pattern that simplifies second-sourcing across vendors. When designing with this device, account for the 55 ns propagation delay in worst-case timing budgets and provide a stable 5V rail with adequate bulk decoupling. For new designs, consider migrating to a MAX II or MAX V CPLD for lower power, faster I/O, and longer-term availability. This page synthesizes distributor stock signals, parametric alternatives, and practical design guidance for the EPM5192LI that goes beyond the legacy datasheet summary.
EPM5192LI-1 - MAX 5000 CPLD, 192 Macrocells, 40MHz, 5V | Altera
The Altera EPM5192LI-1 is a high-speed, high-density CMOS EPLD (Erasable Programmable Logic Device) from the legacy MAX 5000 family, providing 3,750 usable gates organized into 192 macrocells and a maximum toggle frequency of 40 MHz at 5V supply. It is offered in a windowed/UV-erasable ceramic package variant denoted by the JEDEC-style "LI" suffix (ceramic JLCC) and the speed grade "-1". Background: A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic IC that combines the deterministic timing of PAL/GAL architecture with macrocell-based sum-of-products logic. The MAX 5000 family sits between simple PALs and modern FPGAs in the programmable-logic hierarchy: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. The "LI" package is a ceramic JLCC (J-Leaded Chip Carrier) suitable for military and industrial temperature grades where hermeticity matters. Key features of the EPM5192LI-1 include 192 macrocells, 3,750 usable gates, 40 MHz worst-case commercial toggle frequency, 5V single-supply operation, 100% tested AC and DC parameters, and a programmable interconnect array (PIA) that routes any macrocell output to any I/O pin. The device is fabricated in 0.7 micron CMOS technology with UV-erasable EPROM cells, allowing multiple design iterations through windowed erasure. It is supported by Altera's legacy MAX+PLUS II development toolchain. The architecture separates I/O from logic via a global PIA, which guarantees predictable, pin-to-pin deterministic propagation delays of approximately 20-25 ns at the -1 speed grade. Each macrocell contains a programmable AND/OR array, a flip-flop with selectable D/T/JK/RS modes, and a configurable output enable. This structure is well-suited to glue-logic, bus-interface, and state-machine applications where predictable timing and instant-on behavior outweigh the absolute gate density. Typical applications include legacy 5V bus-interface bridges, military and avionics replacement programs, factory automation controllers, and printed-circuit-board glue logic for address decoding, interrupt arbitration, and register-based state machines. The ceramic windowed package and industrial/military temperature capability also make it a strong choice for long-lifecycle defense platforms that must match obsolete system-level form factors. Design consideration: the "LI" suffix denotes a ceramic windowed JLCC package with military-grade screening; engineers targeting commercial boards should evaluate the plastic JEDEC variants (e.g., EPM5192LC-1) for cost reasons, while keeping the EPM5192LI-1 reserved for harsh-environment or radiation-tolerant designs. This page synthesizes distributor pricing, verified drop-in same-package alternatives from the Site MPN list, and practical design notes not consolidated in the manufacturer datasheet.
EPM5192LI-2 - 192-Macrocell MAX 5000 PLD | Altera | 84-Pin PLCC
The Altera EPM5192LI-2 is a high-speed, high-density CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, delivering 192 macrocells, 64 I/O lines, and a tpd of 55 ns in an 84-pin PLCC (JEDEC S-PQCC-J84) package. It is the lower-power LI suffix variant and the speed grade -2 derivative of the EPM5192 base device, optimized for industrial temperature operation (-40 C to +85 C) on a 4.5 V to 5.5 V single supply. What is a MAX 5000 device? The Altera MAX (Multiple Array matriX) 5000 series is a classic UV-erasable/OTP Complex Programmable Logic Device (CPLD) family, sitting in the PLD hierarchy between simple PAL/GAL SPLDs and modern SRAM-based FPGAs. Architecturally, a MAX 5000 CPLD partitions logic into interconnected Logic Array Blocks (LABs), each containing a programmable AND/OR array feeding multiple macrocells with configurable flip-flops. Compared to a discrete PAL, a MAX 5000 CPLD provides higher density, predictable timing, and non-volatile (UV-erasable) configuration, while remaining far simpler than an FPGA - no external boot PROM, deterministic pin-to-pin delays, and a unified 5 V supply rail. Key features of the EPM5192LI-2 include 192 macrocells organized into 12 LABs, 72 total inputs (7 dedicated + 64 I/O), 64 user I/O lines, 55 ns pin-to-pin propagation delay, and 100 MHz internal counter frequency. Power consumption is typically 600 mW at 5 V/25 C, and the device supports in-system programming via Altera's MAX+plus II design toolchain. The 84-pin PLCC (J-lead) package offers a socket-compatible upgrade path for legacy designs. From an architectural standpoint, the EPM5192LI-2 uses Altera's classic EEPROM/UV configuration cell with a fast programmable interconnect (PIA) that routes signals between LABs. Each macrocell includes a product-term steering logic block, a programmable flip-flop (D/T/JK), and a user-configurable I/O architecture, giving the designer dense combinational plus registered logic without external glue. The -2 speed grade and the -LI (lower-power, industrial-temperature) suffix make this part well-suited for designs that previously used a 74-series TTL/SPLD combination but now require more logic per board. Typical applications include industrial control glue logic, address decoding in microprocessor/DSP systems, bus interfacing (e.g., ISA, PC/104, VME), state-machine controllers, peripheral replacement, and legacy telecom backplane logic. The 192-macrocell density suits designs that previously required multiple PALs or discrete SSI/MSI logic. When designing with the EPM5192LI-2, engineers should budget the device's worst-case Icc of approximately 600 mW and verify timing with MAX+plus II timing simulation, since the 55 ns tpd directly limits clock frequency at 18 MHz. The 84-pin PLCC package is windowed ceramic or OTP plastic; ensure your programmer supports the EPM5192 JEDEC file format. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 5000 family and the wider Classic PLD ecosystem, and practical design notes that go beyond the manufacturer datasheet's quick-reference tables.
EPM5192LI84 - 192-Macrocell MAX 5000 CPLD 84-PLCC | Altera
The Altera EPM5192LI84 is a UV-Erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 family, providing 192 macro cells and 3,750 usable gates in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It operates from a single 5 V supply and supports a pin-to-pin propagation delay of approximately 25 ns, with a maximum toggle frequency of 40 MHz. The LI84 suffix indicates the industrial temperature grade (-40 °C to +85 °C) and the J-lead PLCC J84 package code (QCCJ). A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-based logic device that implements glue logic, state machines, bus decoding, and interface bridging functions between fixed-function ICs. The MAX 5000 family sits within Altera's broader programmable logic hierarchy: CPLD -> Programmable Logic Device (PLD) -> Programmable Logic -> Digital Semiconductor. CPLDs are distinguished from FPGAs by their deterministic timing, instant-on non-volatile configuration, and pin-to-pin delay specifications that do not vary with logic utilization. Key features of the EPM5192LI84 include 192 macro cells, 3.75 K usable gates, 64 user I/O pins, a JTAG-based in-system programming interface (not all variants), and an OTP/UV-erasable configuration memory that retains pattern data without external storage. The PLCC-84 socket-compatible package is removable for laboratory UV erasure and re-programming, which historically made this family attractive for prototyping and low-volume industrial designs. The device uses Altera's classic MAX architecture with an EEPROM/EPROM-based AND plane feeding a fixed OR-plane macro cell fabric. Each macro cell contains a programmable flip-flop, product-term selection logic, and an I/O control block. Logic synthesis is performed with Altera's MAX+PLUS II or Quartus design tools, which are still maintained in legacy mode for industrial customers servicing long-lifecycle equipment. Typical applications include legacy industrial control replacement, military/aerospace avionics refresh (via the JM/883 MIL-STD-883B variants), telecommunications backplane glue logic, and bus-interface bridging in long-lifecycle OEM equipment. The OTP nature makes the EPM5192LI84 suited to designs where the pattern is finalized and re-programming is rarely required. When designing with this part, note that the LI84 device does NOT support in-system programmability - the JTAG port is absent on most MAX 5000 OTP variants, so a stand-alone programmer (e.g. Altera Logic Programmer or compatible third-party tools) is required. Use the LC84 (windowed ceramic) variant if UV erasure is anticipated, and reserve proper decoupling on every VCC/ground pin pair to meet the 5 V TTL I/O switching noise budget. This page synthesizes distributor pricing snapshots, same-brand pin-compatible variants already published on XAIPART (EPM5192LI family members), and practical design notes not found in the legacy Altera datasheet alone.
EPM5192QC-1 - 192-Macrocell MAX 5000 OTP PLD, 40ns, PQFP-100 | Altera
The Altera EPM5192QC-1 is a 192-macrocell high-speed, high-density CMOS Erasable Programmable Logic Device (PLD) from the MAX 5000 family, packaged in a 100-pin PQFP (R-PQFP-G100) with gull-wing terminals and a 0.650 mm lead pitch. The device features a 40 ns propagation delay (tPD) in the -1 speed grade and supports a maximum clock frequency of 50 MHz, making it suitable for glue-logic, bus decoding, and state-machine integration in legacy 5V systems. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is configured by the end user after manufacture. Within the broader taxonomy, MAX 5000 devices belong to the One-Time-Programmable (OTP) windowless PLD family, sitting between simple SPLDs and high-density CPLDs/FPGAs in density. They are organized as interconnected Logic Array Blocks (LABs) joined by a Programmable Interconnect Array (PIA), with the EPM5192QC-1 implementing 12 LABs and a shared external clock input feeding all macrocells. Key specifications include 192 macrocells, 64 user I/O lines, 7 dedicated inputs, a 5 V supply range of 4.75 V to 5.25 V, and a -1 speed grade delivering 40 ns pin-to-pin delay. The OTP EPROM-style configuration cell eliminates window erasure and supports surface-mount assembly without quartz erase windows, unlike earlier UV-erasable MAX parts. Architecturally, the EPM5192QC-1 uses a sum-of-products macrocell with a programmable AND/OR plane feeding a configurable output register. Each macrocell supports combinational or registered operation with feedback, and the PIA routes every LAB signal to every other LAB for full connectivity. The shared clock pin and dedicated clock-enable network simplify synchronous design across all 192 flip-flops. Typical applications include 5V microprocessor peripheral decoding, address/data bus arbitration, DMA/state-machine controllers, industrial control glue logic, and legacy telecom backplane glue. The PQFP-100 footprint is widely supported on through-hole adapters for retrofit designs. When designing with this device, ensure that switching noise on the 5 V rail does not exceed the 5.25 V abs-max rating, and use a high-frequency decoupling network (0.1 uF + 10 uF) within 5 mm of every VCC/ground pair to meet tPD specifications under full I/O switching load. This page synthesizes drop-in alternative listings (EPM5192QC, EPM5192AQC-1, EPM5192AQC-2 from the same die and package) and pricing/availability context not found in the manufacturer datasheet alone. Engineers evaluating second-source or speed-grade substitutes for legacy 5V PLD sockets can use the alternatives list to identify pin-compatible drop-ins without PCB rework.
EPM570F100A5N - MAX II CPLD, 570 LE, 100-FBGA | Intel / Altera
The Intel (formerly Altera) EPM570F100A5N is a MAX II family Complex Programmable Logic Device (CPLD) delivering 570 Logic Elements, 440 macrocells, and a 5.4 ns pin-to-pin logic delay in a 100-ball FineLine BGA (FBGA-100) package. According to the manufacturer datasheet, the device is fabricated on a 0.18 µm non-volatile flash process and supports user I/O operation at 1.5 V, 1.8 V, 2.5 V, and 3.3 V with multi-voltage core/IO bank support. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses a combination of AND/OR arrays and macrocells to implement combinational and sequential logic. In the broader programmable logic hierarchy, a CPLD sits between small PAL/GAL devices and large FPGAs, offering instant-on non-volatile configuration, deterministic timing, and high pin-to-pin speed. The MAX II family is positioned as a low-cost, low-power glue-logic replacement for discrete MSI/SSI TTL parts. Key features include 8 Kbits of user flash memory, JTAG IEEE 1149.1 boundary-scan and in-system programmability (ISP), a 4-line global clock network, 66 MHz 32-bit PCI-compliant I/O, and standby current under 100 µA. The device supports Schmitt-trigger inputs and hot-socketing, enabling live insertion into backplane applications. The FBGA-100 package exposes up to 76 user I/O pins. The MAX II architecture uses a MultiVolt core with a 3.3 V core and bank-based I/O voltages selectable per bank. Designers configure the device through JTAG or the Altera/Quartus programming tools using the IEEE 1532 or Jam STAPL flow. The non-volatile flash configuration cell eliminates the external boot PROM required by SRAM FPGAs, simplifying board design. Typical applications include bus-interface bridging (e.g., I2C/SPI to parallel GPIO expansion), power-sequencing and reset-distribution logic, address decoding for memory-mapped SoCs, industrial control glue logic, and automotive body electronics. The -A5N speed/temperature grade provides 0 to 85 °C commercial operation at the 5.4 ns tPD timing bin. When designing, allocate decoupling on every VCCIO bank and use the dedicated GND balls for low-inductance return paths. The Quartus II / Quartus Prime toolchain provides pre-compiled MAX II library elements to simplify logic entry. This page synthesizes distributor pricing, drop-in alternatives, and design notes not consolidated in the manufacturer datasheet.
EPM570F100C4N - MAX II CPLD, 440 LEs, 100-FBGA | Intel
The Intel EPM570F100C4N is a MAX II family Complex Programmable Logic Device (CPLD) featuring 440 Logic Elements (LEs), 80 user I/O pins, and a 5.4 ns pin-to-pin propagation delay, housed in a 100-ball FineLine BGA (FBGA) package. Part of Intel's (formerly Altera's) non-volatile MAX II series, it combines instant-on Flash-based configuration with the simplicity of a low-power CPLD, eliminating the external configuration memory that older CPLDs required. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device built from a small number of macrocells organized into logic array blocks, designed to replace discrete glue-logic ICs with high-speed combinational and registered logic. CPLDs sit in the programmable logic hierarchy below FPGAs, offering lower logic density but deterministic timing, faster I/O response, and instant-on operation. MAX II devices extend this category with lower static power, higher I/O count per package, and a multi-volt core (3.3 V core / 1.8 V internal) compared with legacy MAX series. Key features include 440 Logic Elements, 4.4 Kbits of user Flash memory, support for hot-socketing, JTAG boundary-scan testing (IEEE 1149.1), and MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfacing. The 100-FBGA package provides high-density board mounting while maintaining a 11 mm x 11 mm footprint, with commercial temperature grade (0C to +85C). The EPM570F100C4N is built on a 0.18 um Flash-based process with an internal 3.3 V regulator. Its deterministic timing architecture delivers predictable pin-to-pin delays independent of routing, making it well-suited for control-plane glue logic where designers require guaranteed response times rather than statistical timing closure. The 80 user I/Os include support for PCI-compatible signaling at 3.3 V, Schmitt trigger inputs, and bus-hold circuitry. Typical applications include bus interface bridging, I/O expansion for microcontrollers, address decoding and glue-logic replacement, LED display control, and power-up sequencing in multi-rail systems. The instant-on (less than 1 ms) configuration time makes it ideal as a boot-loader companion to FPGAs or microcontrollers. When designing, ensure I/O bank supply voltages match the driven peripherals and place decoupling capacitors as close as possible to the VCCIO and VCCINT pins. Use Quartus II or the free Quartus Prime Lite for synthesis, fitting, and JTAG programming via the ByteBlaster II or USB-Blaster download cable. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with all data cross-referenced to the original Altera/Intel MAX II device handbook.
EPM570F100C5N - 570 LE MAX II CPLD 100-FBGA | Intel / Altera
The Altera (Intel) EPM570F100C5N is a MAX II family instant-on, non-volatile CPLD with 570 logic elements, 440 macrocells, and 76 user I/Os, fabricated on a 0.18-micron CMOS process and housed in a 100-ball FineLine BGA (FBGA-100) package measuring 11 x 11 mm with 1.0 mm ball pitch. It supports internal supply rails of 2.5 V and 3.3 V with a 5.4 ns pin-to-pin logic delay, and operates across the commercial 0C to 85C junction temperature range. The MAX II architecture replaces legacy EPROM/EPLD technology with on-chip Flash configuration memory, giving the device instant-on behavior at power-up with no external boot PROM required. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PLDs and high-density FPGAs in the programmable logic hierarchy. MAX II CPLDs use a unified Logic Array Block (LAB) architecture combined with a multi-level interconnect, providing deterministic timing ideal for glue logic, bus decoding, interface bridging, and control-plane state machines. Unlike SRAM-based FPGAs, the non-volatile Flash configuration makes MAX II parts boot in microseconds and retain their bitstream through power cycles without an external configuration device. Key features of the EPM570F100C5N include 76 user I/Os, an 8 Kbit user Flash memory block (UFM), in-system programmability via JTAG, multi-volt core/IO support (1.8 V, 2.5 V, 3.3 V I/O standards), and a MultiVolt core that allows the core to run at 3.3 V while I/O banks operate at mixed voltages. The 100-FBGA package delivers the highest I/O count in the EPM570 family, making it suitable for I/O-rich glue-logic designs where board space is constrained. Typical applications for the EPM570F100C5N include bus interface bridging (e.g., PCI to local bus), address decoding and chip-select generation in microprocessor systems, LED display driving and scan-matrix control, peripheral I/O expansion, and as a low-power alternative to small FPGAs in cost-sensitive industrial designs. Designers value MAX II CPLDs for deterministic timing, low static power (typically under 50 mA Icc), and instant-on behavior that eliminates FPGA configuration delay. Designers should pay attention to MultiVolt bank configuration when mixing 1.8 V, 2.5 V, and 3.3 V interfaces; ensure the JTAG chain is properly terminated with 4.7 kohm pull-ups on TCK/TMS/TDI; and verify signal integrity on high-speed clock inputs to avoid metastability. The 100-FBGA requires careful PCB layout with microvia or via-in-pad technology for reliable solder joints. This page synthesizes distributor pricing, drop-in replacement alternatives, and practical design notes not found on a single datasheet, providing engineers with a complete procurement and substitution reference.
EPM570F100I5 - MAX II CPLD, 440 LE, 76 I/O, 100-FBGA | Intel
The Intel (formerly Altera) EPM570F100I5 is a MAX II family Complex Programmable Logic Device (CPLD) featuring 440 logic elements, 76 user I/Os, and 201.1 MHz maximum internal frequency, packaged in a 100-ball FineLine BGA (FBGA-100). It is fabricated on a 0.18 µm process and supports 2.5 V / 3.3 V mixed-voltage operation for the core and I/O banks. The MAX II architecture is built on a non-volatile Flash look-up table (LUT) array with instant-on functionality and in-system programmability via JTAG (IEEE Std. 1149.1). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the hierarchy between simple glue-logic PAL/GAL chips and large FPGAs. CPLDs use a programmable AND/OR array with non-volatile configuration memory, providing deterministic, single-clock-cycle propagation delays and instant power-on behavior. MAX II devices specifically use a LUT-based architecture (rather than classic PLA) combined with on-chip Flash configuration to deliver FPGA-like density at CPLD-like simplicity - making them ideal for I/O expansion, bus bridging, interface protocol translation, and power-sequencing logic that must be active immediately at system power-up. Key features of the EPM570F100I5 include 440 logic elements (LEs), 440 macrocells, 76 user I/O pins, and an internal operating frequency of 201.1 MHz. The device integrates 8 Kbits of user Flash memory (UFM) for storing non-volatile data such as serial numbers, calibration constants, or boot parameters. Multi-voltage I/O banks support 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfaces, allowing direct connection to legacy 5 V-tolerant buses through proper external components. The JTAG-based in-system programmability (ISP) eliminates the need for a separate boot PROM and supports IEEE 1149.1 boundary-scan testing. Architecturally, the MAX II device uses a uniform interconnect matrix that routes LUT outputs to I/O pins with predictable, fast timing. Every LE includes a 4-input LUT, a programmable register, and a carry chain. The integrated Flash configuration block is in-system programmable through JTAG and supports JTAG-based verification during production test. The UFM block provides a small non-volatile memory that can be accessed from user logic, eliminating the need for a separate EEPROM in many designs. Typical applications of the EPM570F100I5 include I/O expansion and level translation in industrial control systems, bus protocol bridging (I2C-to-SPI, UART-to-PCI), LED display and lighting control sequencing, power-supply management and hot-swap control logic, JTAG-based test access port (TAP) multiplexing, and general glue-logic replacement in consumer and embedded designs. The instant-on, deterministic-timing characteristics make it especially valuable in power-rail sequencing for processor cores, memory subsystems, and complex SoCs that require controlled bring-up. When designing with the EPM570F100I5, pay careful attention to the FBGA-100 PCB footprint - a 1.0 mm ball pitch requires precise land pattern design and reflow profile control. Use the Altera/Intel Quartus II design software (legacy) or Quartus Prime to develop, simulate, and program the device; the JTAG interface supports in-system programming after PCB assembly. Provide proper decoupling on each VCCINT and VCCIO bank and follow Intel's recommended BGA routing escape pattern to minimize via stubs and signal-integrity issues on high-speed outputs. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical BGA-layout design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and designing with the EPM570F100I5.
EPM570F100I5N - 570 LEs CPLD, 100-FBGA, 5.4ns | Intel / Altera
The Intel (formerly Altera) EPM570F100I5N is a non-volatile Flash-based Complex Programmable Logic Device (CPLD) from the MAX II family, integrating 570 Logic Elements (LEs), 440 macrocells, and 76 programmable I/Os in a 100-ball FineLine BGA package. It supports 8.7 ns pin-to-pin propagation delay, 304 MHz maximum internal frequency, and operates from a single 2.5 V/3.3 V core supply (2.375 V to 3.6 V) with 55 mA typical ICC. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that sits in the broader hierarchy of programmable logic families: CPLD -> Programmable Logic Device (PLD) -> Digital Logic IC -> Semiconductor. Compared with SRAM-based FPGAs, CPLDs like the MAX II family use Flash configuration memory, providing instant-on operation in <1 ms and eliminating the need for external boot PROMs. They are typically used as glue logic, interface bridges, and bus controllers where deterministic timing, low power, and instant wake-up are required. Key features of the EPM570F100I5N include MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfaces on the same die, in-system programmability via JTAG (IEEE 1149.1), 8 Kbits of user Flash memory, and four global routing clocks. The device supports hot-socketing and I/O tri-state during power-up, enabling live insertion into backplane designs without disturbing system operation. Architecturally, the MAX II family uses a Logic Array Block (LAB) structure with 10 LEs per LAB and a continuous FastTrack interconnect, providing predictable, deterministic timing paths. The non-volatile Flash cell stores the configuration, allowing 100% factory retention after >10,000 program/erase cycles. The 100-FBGA (11x11 mm) package is compatible with the MAX II G family upgrade path. Typical applications include I/O expansion and bus bridging in industrial control, glue logic for microcontrollers/ASICs, power-up sequencing, LED and display control, and FPGA configuration memory replacement. In telecommunications and white-goods designs, the EPM570F100I5N serves as a deterministic-timing state-machine controller. When designing with this device, ensure JTAG chain integrity by adding proper TCK pull-down and TMS pull-up resistors, and respect the 3.6 V absolute maximum VCCINT to avoid permanent Flash corruption. Verify the I/O bank voltage compatibility against mixed-voltage peripherals before layout finalization. This page synthesizes distributor pricing, drop-in upgrade alternatives within the MAX II family, and practical design notes not found in the manufacturer datasheet.
EPM570F256C3 - MAX II CPLD, 440 Logic Elements, 256-FBGA | Intel
The Intel (formerly Altera) EPM570F256C3 is a MAX II family non-volatile, instant-on Complex Programmable Logic Device (CPLD) with 440 macro cells/Logic Elements, 304 MHz internal performance, and a 256-ball FineLine BGA package, fabricated on a 0.18 µm process. It supports 2.5 V and 3.3 V external supply operation (multi-volt core I/O) and is one of the lowest-power, lowest-cost CPLDs in the Altera/Intel MAX II lineup. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device containing multiple macro cells interconnected by a programmable AND/OR array. CPLDs are commonly positioned between discrete logic ICs (low density) and FPGAs (high density) in the broader programmable logic hierarchy: glue logic -> PLD -> CPLD -> FPGA. They are valued for deterministic pin-to-pin propagation delays (typically 4-7 ns), instant-on behavior from on-chip flash configuration memory, and ability to replace many discrete 74-series logic chips with a single device. Key features include 440 Logic Elements organized across 570 equivalent macro cells, an 80 user I/O count, 8 Kbits of user flash memory, in-system programmability via JTAG (IEEE 1149.1), multi-volt core and I/O support (1.8 V/2.5 V/3.3 V), and a 17 mm × 17 mm FineLine BGA package. The device also offers 4-input look-up tables, expansion factor, expansion sharing, and a built-in oscillator. The EPM570F256C3 uses Altera's classic MAX II architecture: a logic array block (LAB) based fabric with non-volatile flash configuration memory enabling sub-100 µs power-on configuration. The MultiVolt I/O architecture supports interfacing with 1.8 V, 2.5 V, and 3.3 V devices on the same board, while the MultiVolt core supports 2.5 V/3.3 V operation. Quartus II (legacy) or Quartus Prime design software is used for development. Typical applications include I/O expansion and bus bridging, power-up sequencing for multi-rail systems, glue logic replacement for 74-series TTL, motor control state machines, and LED display driver logic. The instant-on non-volatile configuration makes it ideal for deterministic boot-time behavior in industrial and automotive subsystems. When designing with this device, route all JTAG signals (TCK, TMS, TDI, TDO, nCE) cleanly and tie unused I/Os to a defined logic state. Provide at least one 0.1 µF decoupling capacitor per power pin pair and follow Intel/Altera AN-441 guidelines for BGA fanout. This page synthesizes verified distributor pricing, drop-in alternatives drawn from the same MAX II family, and practical design notes not found in the manufacturer datasheet alone.