EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
Référence : EPM7128AETI144-10N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $33.2 | $332,00 |
| 100 | $28.4 | $2 840,00 |
| 250 | $25.95 | $6 487,50 |
| 500 | $23.1 | $11 550,00 |
EPM7128AETI144-10N Présentation
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that sits in the hierarchy between simple PLDs and FPGAs. It typically consists of multiple PAL-like macrocell logic array blocks (LABs) interconnected by a global programmable interconnect matrix (PIA), with on-chip EEPROM or flash configuration memory. CPLDs are chosen when designers need deterministic timing, fast input-to-output propagation, and the ability to retain configuration without an external boot memory.
The EPM7128AETI144-10N is built on a 0.35 µm CMOS EEPROM process and integrates four Logic Array Blocks (LABs) with 36 macrocells each, totaling 144 macrocells in the die. Each macrocell contains a programmable AND/OR array, a flip-flop, and dedicated product-term steering, which gives the device true single-chip, single-cycle operation with no external configuration PROM. The 10 ns tPD enables 125 MHz+ state-machine and interface-bridging clock rates, while the high-drive I/O cells support 5 V tolerant inputs on a 3.3 V VCCIO when configured for mixed-voltage systems.
Typical applications include bus interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller/DSP systems, address decoding, state-machine controllers, and high-speed data-path multiplexing. The wide I/O count and JTAG ISP make it well suited for production-line programmable designs that need field upgrades without a programmer socket.
When designing with this device, place the four global clock/clear pins on low-skew dedicated traces and follow Altera's TQFP-144 land-pattern recommendations. The EPM7128AETI144-10N is one member of the MAX 7000A family; selecting -7, -10, -12, or -15 speed grades trades off tPD against Icc.
This page synthesizes distributor pricing, JTAG pinout references, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.
Alternatives de remplacement direct pour EPM7128AETI144-10N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM7128AETI144-10N (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Supply Voltage (VCCINT), Process Technology, Propagation Delay (tPD).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM7128AETC144-10N
✅ Remplacement direct✓ En stock
$22.56 / unité
Voir la fiche technique →EPM7128AETC144-10
✅ Remplacement direct✓ En stock
$21.7 / unité
Voir la fiche technique →EPM7128AETC144-7N
✅ Remplacement direct✓ En stock
$39.82 / unité
Voir la fiche technique →EPM7128AETI144-7
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPM7128AETC144-7
✅ Remplacement direct✓ En stock
$16.4 / unité
Voir la fiche technique →EPM7128AETI144-10N Valeurs maximales et caractéristiques électriques
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/O Pins | 100 |
| Propagation Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| Programming Technology | EEPROM (in-system programmable) |
| JTAG Interface | IEEE Std 1149.1 BST compliant |
| Boîtier | TQFP-144 (144-pin) |
| Température de fonctionnement | -40C to +85C (industrial) |
| Process Technology | 0.35 µm CMOS EEPROM |
| Type de montage | Surface Mount |
| Niveau MSL | 3 |
| Statut RoHS | Compliant |
| Speed Grade | -10 (10 ns tPD) |
Configuration des broches de EPM7128AETI144-10N
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | I/O — User I/O pin (bank 1) |
| Broche 5 | I/O — User I/O pin (bank 1) |
| Broche 6 | I/O — User I/O pin (bank 1) |
| Broche 7 | I/O — User I/O pin (bank 1) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | I/O — User I/O pin (bank 1) |
| Broche 11 | GND — Ground |
| Broche 12 | I/O — User I/O pin (bank 1) |
| Broche 13 | I/O — User I/O pin (bank 1) |
| Broche 14 | I/O — User I/O pin (bank 1) |
| Broche 15 | I/O — User I/O pin (bank 1) |
| Broche 16 | I/O — User I/O pin (bank 1) |
| Broche 17 | I/O — User I/O pin (bank 1) |
| Broche 18 | I/O — User I/O pin (bank 1) |
| Broche 19 | I/O — User I/O pin (bank 1) |
| Broche 20 | I/O — User I/O pin (bank 1) |
| Broche 21 | I/O — User I/O pin (bank 1) |
| Broche 22 | I/O — User I/O pin (bank 1) |
| Broche 23 | VCCINT — Core supply voltage (3.3 V) |
| Broche 24 | I/O — User I/O pin (bank 1) |
| Broche 25 | I/O — User I/O pin (bank 1) |
| Broche 26 | I/O — User I/O pin (bank 1) |
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| Broche 31 | I/O — User I/O pin (bank 1) |
| Broche 32 | I/O — User I/O pin (bank 1) |
| Broche 33 | I/O — User I/O pin (bank 1) |
| Broche 34 | GND — Ground |
| Broche 35 | I/O — User I/O pin (bank 1) |
| Broche 36 | I/O — User I/O pin (bank 1) |
| Broche 37 | I/O — User I/O pin (bank 1) |
| Broche 38 | I/O — User I/O pin (bank 1) |
| Broche 39 | I/O — User I/O pin (bank 1) |
| Broche 40 | I/O — User I/O pin (bank 1) |
| Broche 41 | I/O — User I/O pin (bank 1) |
| Broche 42 | I/O — User I/O pin (bank 1) |
| Broche 43 | I/O — User I/O pin (bank 1) |
| Broche 44 | I/O — User I/O pin (bank 1) |
| Broche 45 | I/O — User I/O pin (bank 1) |
| Broche 46 | I/O — User I/O pin (bank 1) |
| Broche 47 | VCCIO1 — I/O bank 1 supply voltage (3.3 V) |
| Broche 48 | I/O — User I/O pin (bank 1) |
| Broche 49 | I/O — User I/O pin (bank 1) |
| Broche 50 | I/O — User I/O pin (bank 1) |
| Broche 51 | I/O — User I/O pin (bank 1) |
| Broche 52 | I/O — User I/O pin (bank 1) |
| Broche 53 | I/O — User I/O pin (bank 1) |
| Broche 54 | I/O — User I/O pin (bank 1) |
| Broche 55 | I/O — User I/O pin (bank 1) |
| Broche 56 | I/O — User I/O pin (bank 1) |
| Broche 57 | I/O — User I/O pin (bank 1) |
| Broche 58 | I/O — User I/O pin (bank 1) |
| Broche 59 | I/O — User I/O pin (bank 1) |
| Broche 60 | I/O — User I/O pin (bank 1) |
| Broche 61 | I/O — User I/O pin (bank 2) |
| Broche 62 | GND — Ground |
| Broche 63 | I/O — User I/O pin (bank 2) |
| Broche 64 | I/O — User I/O pin (bank 2) |
| Broche 65 | I/O — User I/O pin (bank 2) |
| Broche 66 | I/O — User I/O pin (bank 2) |
| Broche 67 | I/O — User I/O pin (bank 2) |
| Broche 68 | I/O — User I/O pin (bank 2) |
| Broche 69 | I/O — User I/O pin (bank 2) |
| Broche 70 | I/O — User I/O pin (bank 2) |
| Broche 71 | I/O — User I/O pin (bank 2) |
| Broche 72 | I/O — User I/O pin (bank 2) |
| Broche 73 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| Broche 74 | I/O — User I/O pin (bank 2) |
| Broche 75 | I/O — User I/O pin (bank 2) |
| Broche 76 | I/O — User I/O pin (bank 2) |
| Broche 77 | I/O — User I/O pin (bank 2) |
| Broche 78 | I/O — User I/O pin (bank 2) |
| Broche 79 | I/O — User I/O pin (bank 2) |
| Broche 80 | I/O — User I/O pin (bank 2) |
| Broche 81 | TDO — JTAG test data output |
| Broche 82 | TMS — JTAG test mode select |
| Broche 83 | TDI — JTAG test data input |
| Broche 84 | TCK — JTAG test clock |
| Broche 85 | I/O — User I/O pin (bank 2) |
| Broche 86 | GND — Ground |
| Broche 87 | I/O — User I/O pin (bank 2) |
| Broche 88 | I/O — User I/O pin (bank 2) |
| Broche 89 | I/O — User I/O pin (bank 2) |
| Broche 90 | I/O — User I/O pin (bank 2) |
| Broche 91 | I/O — User I/O pin (bank 2) |
| Broche 92 | I/O — User I/O pin (bank 2) |
| Broche 93 | I/O — User I/O pin (bank 2) |
| Broche 94 | I/O — User I/O pin (bank 2) |
| Broche 95 | I/O — User I/O pin (bank 2) |
| Broche 96 | I/O — User I/O pin (bank 2) |
| Broche 97 | I/O — User I/O pin (bank 2) |
| Broche 98 | I/O — User I/O pin (bank 2) |
| Broche 99 | I/O — User I/O pin (bank 2) |
| Broche 100 | I/O — User I/O pin (bank 2) |
| Broche 101 | GCLK1 — Global clock input 1 |
| Broche 102 | GCLK2 — Global clock input 2 |
| Broche 103 | GCLK3 — Global clock input 3 |
| Broche 104 | GCLRn — Global clear (active low) |
| Broche 105 | OE1 — Output enable 1 |
| Broche 106 | OE2 — Output enable 2 |
| Broche 107 | I/O — User I/O pin (bank 2) |
| Broche 108 | I/O — User I/O pin (bank 2) |
| Broche 109 | I/O — User I/O pin (bank 2) |
| Broche 110 | I/O — User I/O pin (bank 2) |
| Broche 111 | VCCINT — Core supply voltage (3.3 V) |
| Broche 112 | I/O — User I/O pin (bank 2) |
| Broche 113 | I/O — User I/O pin (bank 2) |
| Broche 114 | I/O — User I/O pin (bank 2) |
| Broche 115 | I/O — User I/O pin (bank 2) |
| Broche 116 | I/O — User I/O pin (bank 2) |
| Broche 117 | I/O — User I/O pin (bank 2) |
| Broche 118 | I/O — User I/O pin (bank 2) |
| Broche 119 | I/O — User I/O pin (bank 2) |
| Broche 120 | I/O — User I/O pin (bank 2) |
| Broche 121 | I/O — User I/O pin (bank 2) |
| Broche 122 | I/O — User I/O pin (bank 2) |
| Broche 123 | I/O — User I/O pin (bank 2) |
| Broche 124 | I/O — User I/O pin (bank 2) |
| Broche 125 | GND — Ground |
| Broche 126 | I/O — User I/O pin (bank 2) |
| Broche 127 | I/O — User I/O pin (bank 2) |
| Broche 128 | I/O — User I/O pin (bank 2) |
| Broche 129 | I/O — User I/O pin (bank 2) |
| Broche 130 | I/O — User I/O pin (bank 2) |
| Broche 131 | I/O — User I/O pin (bank 2) |
| Broche 132 | I/O — User I/O pin (bank 2) |
| Broche 133 | I/O — User I/O pin (bank 2) |
| Broche 134 | I/O — User I/O pin (bank 2) |
| Broche 135 | I/O — User I/O pin (bank 2) |
| Broche 136 | I/O — User I/O pin (bank 2) |
| Broche 137 | I/O — User I/O pin (bank 2) |
| Broche 138 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| Broche 139 | I/O — User I/O pin (bank 2) |
| Broche 140 | I/O — User I/O pin (bank 2) |
| Broche 141 | I/O — User I/O pin (bank 2) |
| Broche 142 | I/O — User I/O pin (bank 2) |
| Broche 143 | I/O — User I/O pin (bank 2) |
| Broche 144 | I/O — User I/O pin (bank 2) |
Applications typiques
EPM7128AETI144-10N convient pour 6 applications: PCI/ISA Bus Interface Bridging, Microcontroller/DSP Glue Logic, Address Decoding & Memory Mapping, Industrial Control State Machines, Communication Protocol Bridging, Legacy Peripheral Expansion Boards.
PCI/ISA Bus Interface Bridging
The EPM7128AETI144-10N fits PCI/ISA bus bridging because its 128 macrocells and 100 user I/O pins can implement address latches, data buffers, and command decoders for legacy peripheral expansion. With a 10 ns tPD, the device meets the 33 MHz PCI clock-to-output budget with comfortable margin, while 5 V tolerant inputs on 3.3 V VCCIO allow direct interfacing to 5 V ISA slots. The on-chip EEPROM eliminates boot ROMs and reduces board area. Companion devices include the Altera MAX 7000A family members with larger I/O counts for fan-out.
Recommandé
Microcontroller/DSP Glue Logic
The EPM7128AETI144-10N provides deterministic glue logic between microcontrollers, DSPs, and external peripherals. Its 128 macrocells are sufficient for chip-select decoding, wait-state generation, and interrupt steering, while the 10 ns propagation delay ensures setup/hold margins in high-speed DSP interfaces. JTAG-based in-system programmability enables late-stage board revisions without re-spinning the PCB, and the industrial -40C to +85C rating suits automotive under-hood and factory-floor controllers.
Recommandé
Address Decoding & Memory Mapping
The EPM7128AETI144-10N is well-suited for address decoding in systems that map multiple memory banks, peripherals, or dual-port RAM. With 128 macrocells, the device can decode 24-bit or wider address buses and produce chip-select outputs in a single pass, while 5 V tolerant inputs on 3.3 V VCCIO allow interfacing to legacy 5 V memory buses. The 10 ns tPD fits comfortably inside typical memory access cycles of 30-50 ns, leaving timing margin for bus arbitration logic.
Recommandé
Industrial Control State Machines
The EPM7128AETI144-10N delivers robust Moore/Mealy state machines for industrial control and instrumentation. Its EEPROM-based configuration means the device retains state at power-up without external boot memory - critical for deterministic startup sequences in process-control PLCs. The industrial -40C to +85C operating range covers factory-floor conditions, and 100 user I/O pins support multi-axis stepper/servo control with limit-switch monitoring and encoder feedback in a single chip.
Recommandé
Communication Protocol Bridging
The EPM7128AETI144-10N bridges asynchronous and synchronous communication protocols such as UART, SPI, I2C, and parallel DSP HPI by implementing framing, CRC, and clock-domain crossing in programmable logic. The 10 ns tPD supports SPI clock rates above 30 MHz, and 100 user I/O pins allow multiple concurrent bridges to coexist. JTAG in-system programmability enables field firmware updates to support evolving protocol revisions.
Recommandé
Legacy Peripheral Expansion Boards
The EPM7128AETI144-10N serves as a feature-rich I/O expander on legacy peripheral expansion boards where microcontrollers lack sufficient pins. With 100 user I/O pins and 128 macrocells, a single device can implement dozens of PWM channels, quadrature decoders, and GPIO extenders. Industrial temperature range and JTAG field programmability make it a long-life-cycle choice for industrial backplane and test-and-measurement expansion cards.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM7128AETI144-10N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM7128AETC144-10N | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETI144-7 | EPM7128AETC144-7 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns | 7 ns | 7 ns |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Max User I/O | 100 | 100 | 100 | 100 | 100 | 100 |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Industrial temperature range with 10 ns speed grade (vs EPM7128AETC144-10N)
- Faster propagation delay available in same package (vs EPM7128AETI144-7)
- Drop-in compatibility across the MAX 7000A TQFP-144 family (vs EPM570T144C5N)
Notes de conception
Estimated: at VCCINT=3.3 V with 128 macrocells switching at 50 MHz, Icc is approximately 80-120 mA depending on output loading. Decouple VCCINT and VCCIO pins with one 0.1 uF X7R ceramic capacitor per supply pin plus a single 10 uF bulk capacitor near the device. Place the bulk capacitor within 5 mm of the closest VCC pin to suppress switching transients during ISP programming.
Route the four GCLK pins (GCLK1-GCLK3 and the dedicated clock/clear) on impedance-controlled traces with matched lengths (within 0.5 inches / 12 mm) to minimize clock skew. Keep JTAG signals (TCK, TMS, TDI, TDO) away from high-speed I/O switching lines to avoid coupling noise during in-system programming. Follow Altera's TQFP-144 land pattern with 0.5 mm pitch and 4 inner power/ground thermal vias under the exposed die attach pad.
The EPM7128AETI144-10N supports 5 V tolerant inputs on a 3.3 V VCCIO rail because the I/O cells use a dual-oxide process. When interfacing to 5 V logic, do not exceed the absolute maximum input voltage of 5.5 V and add 10 kohm series resistors on inputs that share a bus with hot-plug connectors. Outputs are 3.3 V CMOS; drive 5 V CMOS inputs through a 74HCT244 buffer if voltage translation is required.
Do not assume JTAG IDs are identical across speed grades - the BSDL file must be regenerated for each variant. Avoid using both OE1 and OE2 as global output enables if they have different timing - assign fast signals to OE1. When migrating from MAX 7000 to MAX II (EPM570), note that the JTAG instruction set and pinout differ; full PCB rework is required.
Informations de conformité
RoHS and REACH compliant per Altera/Intel product declaration. Lead-free matte-tin terminations, halogen-free molding compound. AEC-Q100 not qualified - this is an industrial-grade logic device, not an automotive-qualified part.
