Altera

EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera

Артикул: EPM7128AETI144-10N ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

3.0 V to 3.6 V (3.3 V nominal) Vdss TQFP-144 (144-pin) Package -10 (10 ns tPD) Speed

От $23.1 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-12

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$38.5	$38,50
10	$33.2	$332,00
100	$28.4	$2.840,00
250	$25.95	$6.487,50
500	$23.1	$11.550,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM7128AETI144-10N Обзор

The Altera (Intel Programmable Solutions Group) EPM7128AETI144-10N is a high-density EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000A family, delivering 128 macrocells, 2,500 usable gates, and a 10 ns pin-to-pin propagation delay in a 144-pin Thin Quad Flat Pack (TQFP-144) industrial-grade package. It features 100 user I/O pins, in-system programmability through the IEEE Std 1149.1 JTAG boundary-scan test interface, and operates from a single 3.0 V to 3.6 V supply with a nominal 3.3 V rail.

A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that sits in the hierarchy between simple PLDs and FPGAs. It typically consists of multiple PAL-like macrocell logic array blocks (LABs) interconnected by a global programmable interconnect matrix (PIA), with on-chip EEPROM or flash configuration memory. CPLDs are chosen when designers need deterministic timing, fast input-to-output propagation, and the ability to retain configuration without an external boot memory.

The EPM7128AETI144-10N is built on a 0.35 µm CMOS EEPROM process and integrates four Logic Array Blocks (LABs) with 36 macrocells each, totaling 144 macrocells in the die. Each macrocell contains a programmable AND/OR array, a flip-flop, and dedicated product-term steering, which gives the device true single-chip, single-cycle operation with no external configuration PROM. The 10 ns tPD enables 125 MHz+ state-machine and interface-bridging clock rates, while the high-drive I/O cells support 5 V tolerant inputs on a 3.3 V VCCIO when configured for mixed-voltage systems.

Typical applications include bus interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller/DSP systems, address decoding, state-machine controllers, and high-speed data-path multiplexing. The wide I/O count and JTAG ISP make it well suited for production-line programmable designs that need field upgrades without a programmer socket.

When designing with this device, place the four global clock/clear pins on low-skew dedicated traces and follow Altera's TQFP-144 land-pattern recommendations. The EPM7128AETI144-10N is one member of the MAX 7000A family; selecting -7, -10, -12, or -15 speed grades trades off tPD against Icc.

This page synthesizes distributor pricing, JTAG pinout references, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.

Аналоги без доработки для EPM7128AETI144-10N — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM7128AETI144-10N (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Supply Voltage (VCCINT), Process Technology, Propagation Delay (tPD).

EPM7128AETC144-10

Altera

Package: 144-pin TQFP (also referred to as LQFP-144)

Operating Temperature: 0C to +70C (Commercial)