Intel

EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera

MPN: EPM9320LC84-20N ✓ Aktif

5 V Vdss Plastic Leaded Chip Carrier (PLCC-84, J-bend) Package 118 MHz Speed

Ajukan Diskon

MOQ: 1 |

Lihat Datasheet (PDF) Lihat Alternatif

Kuantitas

EPM9320LC84-20N Ringkasan

The Intel / Altera EPM9320LC84-20N is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 6,000 usable gates with 320 macrocells in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. Operating from a 5 V supply with a propagation delay of 16 ns (tPD) and an internal frequency up to 118 MHz, this device targets glue-logic, bus-interface, and state-machine consolidation in industrial and commercial systems. According to the manufacturer datasheet, the -20 speed grade corresponds to a 16 ns pin-to-pin delay, placing this part in the standard-performance tier of the MAX 9000 lineup.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a centralized interconnect matrix. The MAX 9000 architecture represents Altera's third-generation Multiple Array MatriX (MAX) implementation, providing predictable timing, in-system programmability via IEEE 1149.1 JTAG, and 5.0-V in-system programmability (ISP). Within the broader taxonomy, the EPM9320LC84-20N belongs to: CPLD -> programmable logic device -> digital IC -> semiconductor.

Key features include 60 user I/O pins, J-bend terminal form with a QCCJ (PLCC) package outline, commercial temperature grading (0C to +70C), and CMOS logic family operation. The device supports 5-V in-system programmability and is built on a 0.5um triple-layer-metal EEPROM process, allowing logic retention without external memory. The 84-pin PLCC package offers a square footprint with 60 usable I/Os plus dedicated programming, JTAG, and power pins.

The MAX 9000 family uses a hierarchical interconnect structure that routes signals between Logic Array Blocks (LABs) and the Programmable Interconnect Array (PIA), delivering consistent timing regardless of design placement. This deterministic timing model is one of the primary reasons CPLDs continue to be selected over FPGAs for fixed-timing glue logic applications such as address decoding, interrupt control, and bus arbitration.

Typical applications include address decoding and bus interface logic in legacy embedded systems, glue logic between microprocessors and peripherals, industrial control boards requiring deterministic timing, state-machine and sequencer implementation, replacement of discrete 74LS/74HC TTL glue, and 5-V tolerant I/O expansion for older MCU designs. The 5-V native I/O is a key reason engineers continue to specify MAX 9000 parts in mixed-voltage designs.

When designing with this device, observe the 5-V VCC requirement and ensure all inputs do not exceed the absolute maximum ratings. Decouple VCC with 0.1uF and 10uF capacitors placed close to the PLCC pins, and use the JTAG port (TMS, TCK, TDI, TDO) for in-system programming. Note that the EPM9320LC84-20N is a mature, long-lived part still widely used for legacy industrial designs.

This page synthesizes distributor pricing, drop-in speed-grade and package alternatives from the MAX 9000 family, and practical design notes not collected in the manufacturer datasheet.

Alternatif penggantian untuk EPM9320LC84-20N — paket yang sama, pin-pada-pin kompatibel. Bagian paket yang berbeda memerlukan kerja ulang PCB diabaikan.

Variasi di dalam seri ini

Model-series yang sama yang kompatibel dengan penggantian EPM9320LC84-20N (sama faktor bentuk dan footprint) — berbeda di dalam Package, Mounting Type, Operating Temperature, Propagation Delay (tPD), Process Technology.

EPM9320ALI84-10N

Altera

Package: 84-pin PLCC (J-lead, 1.270 mm pitch)

Mounting Type: Surface Mount (PLCC socket compatible)

Operating Temperature: -40C to +85C (industrial)