EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
料号： EPM9320LC84-20N ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.75 | $18.75 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $10.25 | $10,250.00 |
EPM9320LC84-20N 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a centralized interconnect matrix. The MAX 9000 architecture represents Altera's third-generation Multiple Array MatriX (MAX) implementation, providing predictable timing, in-system programmability via IEEE 1149.1 JTAG, and 5.0-V in-system programmability (ISP). Within the broader taxonomy, the EPM9320LC84-20N belongs to: CPLD -> programmable logic device -> digital IC -> semiconductor.
Key features include 60 user I/O pins, J-bend terminal form with a QCCJ (PLCC) package outline, commercial temperature grading (0C to +70C), and CMOS logic family operation. The device supports 5-V in-system programmability and is built on a 0.5um triple-layer-metal EEPROM process, allowing logic retention without external memory. The 84-pin PLCC package offers a square footprint with 60 usable I/Os plus dedicated programming, JTAG, and power pins.
The MAX 9000 family uses a hierarchical interconnect structure that routes signals between Logic Array Blocks (LABs) and the Programmable Interconnect Array (PIA), delivering consistent timing regardless of design placement. This deterministic timing model is one of the primary reasons CPLDs continue to be selected over FPGAs for fixed-timing glue logic applications such as address decoding, interrupt control, and bus arbitration.
Typical applications include address decoding and bus interface logic in legacy embedded systems, glue logic between microprocessors and peripherals, industrial control boards requiring deterministic timing, state-machine and sequencer implementation, replacement of discrete 74LS/74HC TTL glue, and 5-V tolerant I/O expansion for older MCU designs. The 5-V native I/O is a key reason engineers continue to specify MAX 9000 parts in mixed-voltage designs.
When designing with this device, observe the 5-V VCC requirement and ensure all inputs do not exceed the absolute maximum ratings. Decouple VCC with 0.1uF and 10uF capacitors placed close to the PLCC pins, and use the JTAG port (TMS, TCK, TDI, TDO) for in-system programming. Note that the EPM9320LC84-20N is a mature, long-lived part still widely used for legacy industrial designs.
This page synthesizes distributor pricing, drop-in speed-grade and package alternatives from the MAX 9000 family, and practical design notes not collected in the manufacturer datasheet.
直接替换替代料： EPM9320LC84-20N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9320LC84-20N （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Operating Temperature, Propagation Delay (tPD), Process Technology.
快速对比工具——选择替代料号进行并排对比：
EPM9320LC84-15
✅ 直接替换✓ 有现货
$17.95 / 个
查看数据手册 →EPM9320LC84-10
✅ 直接替换✓ 有现货
$84.96 / 个
查看数据手册 →EPM9320LC84-20
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EPM9320LI84-20
✅ 直接替换✓ 有现货
$12.8 / 个
查看数据手册 →EPM9320LI84-10N
✅ 直接替换📋 参考替代料（不在目录中）
EPM9320ALI84-10N
✅ 直接替换✓ 有现货
$21.95 / 个
查看数据手册 →EPM9320LC84-20N 最大额定值与电气特性
| Series | MAX 9000 |
| Logic Family | CMOS (EEPROM-based) |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 |
| Macrocells | 320 |
| User I/Os | 60 |
| 引脚数 | 84 |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | QCCJ |
| Propagation Delay (tPD) | 16 ns |
| Internal Frequency | 118 MHz |
| Supply Voltage (VCC) | 5 V |
| 工作温度 | 0 C to +70 C (Commercial) |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| 安装类型 | Surface Mount (J-bend) |
| Terminal Form | J BEND |
EPM9320LC84-20N 引脚配置
| 引脚 1 | I/O — User I/O pin (bank 1) |
| 引脚 2 | I/O — User I/O pin (bank 1) |
| 引脚 3 | I/O — User I/O pin (bank 1) |
| 引脚 4 | I/O — User I/O pin (bank 1) |
| 引脚 5 | I/O — User I/O pin (bank 1) |
| 引脚 6 | I/O — User I/O pin (bank 1) |
| 引脚 7 | I/O — User I/O pin (bank 1) |
| 引脚 8 | I/O — User I/O pin (bank 1) |
| 引脚 9 | I/O — User I/O pin (bank 1) |
| 引脚 10 | I/O — User I/O pin (bank 1) |
| 引脚 11 | I/O — User I/O pin (bank 1) |
| 引脚 12 | GND — Ground |
| 引脚 13 | I/O — User I/O pin (bank 2) |
| 引脚 14 | I/O — User I/O pin (bank 2) |
| 引脚 15 | I/O — User I/O pin (bank 2) |
| 引脚 16 | I/O — User I/O pin (bank 2) |
| 引脚 17 | I/O — User I/O pin (bank 2) |
| 引脚 18 | I/O — User I/O pin (bank 2) |
| 引脚 19 | I/O — User I/O pin (bank 2) |
| 引脚 20 | I/O — User I/O pin (bank 2) |
| 引脚 21 | I/O — User I/O pin (bank 2) |
| 引脚 22 | I/O — User I/O pin (bank 2) |
| 引脚 23 | VCC — +5 V supply |
| 引脚 24 | I/O — User I/O pin (bank 2) |
| 引脚 25 | I/O — User I/O pin (bank 2) |
| 引脚 26 | I/O — User I/O pin (bank 2) |
| 引脚 27 | I/O — User I/O pin (bank 2) |
| 引脚 28 | I/O — User I/O pin (bank 2) |
| 引脚 29 | I/O — User I/O pin (bank 2) |
| 引脚 30 | TDI — JTAG Test Data In |
| 引脚 31 | TMS — JTAG Test Mode Select |
| 引脚 32 | TCK — JTAG Test Clock |
| 引脚 33 | I/O — User I/O pin (bank 3) |
| 引脚 34 | I/O — User I/O pin (bank 3) |
| 引脚 35 | I/O — User I/O pin (bank 3) |
| 引脚 36 | I/O — User I/O pin (bank 3) |
| 引脚 37 | I/O — User I/O pin (bank 3) |
| 引脚 38 | I/O — User I/O pin (bank 3) |
| 引脚 39 | I/O — User I/O pin (bank 3) |
| 引脚 40 | I/O — User I/O pin (bank 3) |
| 引脚 41 | I/O — User I/O pin (bank 3) |
| 引脚 42 | GND — Ground |
| 引脚 43 | I/O — User I/O pin (bank 4) |
| 引脚 44 | I/O — User I/O pin (bank 4) |
| 引脚 45 | I/O — User I/O pin (bank 4) |
| 引脚 46 | I/O — User I/O pin (bank 4) |
| 引脚 47 | I/O — User I/O pin (bank 4) |
| 引脚 48 | I/O — User I/O pin (bank 4) |
| 引脚 49 | I/O — User I/O pin (bank 4) |
| 引脚 50 | I/O — User I/O pin (bank 4) |
| 引脚 51 | I/O — User I/O pin (bank 4) |
| 引脚 52 | I/O — User I/O pin (bank 4) |
| 引脚 53 | I/O — User I/O pin (bank 4) |
| 引脚 54 | VCC — +5 V supply |
| 引脚 55 | I/O — User I/O pin (bank 4) |
| 引脚 56 | I/O — User I/O pin (bank 4) |
| 引脚 57 | I/O — User I/O pin (bank 4) |
| 引脚 58 | I/O — User I/O pin (bank 4) |
| 引脚 59 | I/O — User I/O pin (bank 4) |
| 引脚 60 | I/O — User I/O pin (bank 4) |
| 引脚 61 | I/O — User I/O pin (bank 5) |
| 引脚 62 | I/O — User I/O pin (bank 5) |
| 引脚 63 | GND — Ground |
| 引脚 64 | I/O — User I/O pin (bank 5) |
| 引脚 65 | I/O — User I/O pin (bank 5) |
| 引脚 66 | I/O — User I/O pin (bank 5) |
| 引脚 67 | I/O — User I/O pin (bank 5) |
| 引脚 68 | I/O — User I/O pin (bank 5) |
| 引脚 69 | I/O — User I/O pin (bank 5) |
| 引脚 70 | I/O — User I/O pin (bank 5) |
| 引脚 71 | I/O — User I/O pin (bank 5) |
| 引脚 72 | I/O — User I/O pin (bank 5) |
| 引脚 73 | I/O — User I/O pin (bank 5) |
| 引脚 74 | I/O — User I/O pin (bank 5) |
| 引脚 75 | VCC — +5 V supply |
| 引脚 76 | I/O — User I/O pin (bank 6) |
| 引脚 77 | I/O — User I/O pin (bank 6) |
| 引脚 78 | I/O — User I/O pin (bank 6) |
| 引脚 79 | I/O — User I/O pin (bank 6) |
| 引脚 80 | I/O — User I/O pin (bank 6) |
| 引脚 81 | I/O — User I/O pin (bank 6) |
| 引脚 82 | I/O — User I/O pin (bank 6) |
| 引脚 83 | TDO — JTAG Test Data Out |
| 引脚 84 | I/O — User I/O pin (bank 6) |
典型应用
EPM9320LC84-20N 适用于 6 应用s: Address Decoding & Bus Interface Logic, Glue Logic Replacement for Discrete TTL, Industrial Control Board Logic, State Machine & Sequencer Implementation, Legacy Microcontroller I/O Expansion, Telecom Backplane & Bus Arbitration.
Address Decoding & Bus Interface Logic
The EPM9320LC84-20N is widely deployed as the central address decoder and bus-interface glue between microprocessors, memory, and peripherals in legacy embedded boards. Its 60 user I/Os and 320 macrocells provide enough logic capacity to decode a full 24-bit address bus plus generate chip-select strobes for SRAM, ROM, and peripheral banks. The 16 ns tPD ensures clean chip-select timing at system clock rates up to ~60 MHz, well matched to 8051, 68k, and early ARM7 designs. Unlike an FPGA, the CPLD's deterministic timing means the chip-select setup and hold are guaranteed regardless of design density, removing a key verification burden for the hardware engineer.
推荐
Glue Logic Replacement for Discrete TTL
Engineers use the EPM9320LC84-20N to consolidate dozens of 74LS, 74HC, and 74FTTL packages into a single 5-V tolerant CPLD, dramatically reducing board area and BOM cost. With 320 macrocells equivalent to roughly 50-80 standard TTL gates per macrocell, the device can absorb entire address-latch, bus-buffer, and interrupt-controller sub-systems. The 5-V native I/Os interface directly to legacy peripherals without level shifters, and the in-system programmability allows last-minute logic fixes without board re-spin. Compared to a discrete TTL implementation, the CPLD reduces power, improves noise margin, and provides testable JTAG access to internal nodes.
推荐
Industrial Control Board Logic
In industrial control cabinets, the EPM9320LC84-20N serves as the deterministic logic core that processes sensor inputs, drives relay and MOSFET control outputs, and sequences power-up events. Its commercial 0C to +70C temperature range fits most factory-floor enclosures, while the industrial -LI84-20 variant extends to -40C to +85C for outdoor installations. The 60 I/Os handle multiple encoder, limit-switch, and optocoupler interfaces in parallel, and the EEPROM-based configuration retains logic state across power cycles for fail-safe recovery. Compared with microcontrollers, the CPLD's predictable timing is preferred for safety-critical interlock logic where software timing variance is unacceptable.
推荐
State Machine & Sequencer Implementation
The EPM9320LC84-20N is well suited to implementing complex multi-state control sequencers for power-supply start-up, motor commutation, and protocol handshaking. With 320 macrocells the device can hold 20-30 large state machines simultaneously, each guaranteed by the MAX 9000 deterministic timing model. The 16 ns tPD provides 60 MHz+ state-transition bandwidth, sufficient for high-speed serial protocol state machines (UART, SPI, I2C master). Non-volatile EEPROM configuration ensures the state machine resumes correctly after power-loss without external boot memory. This application pattern is common in telecom and instrumentation designs.
推荐
Legacy Microcontroller I/O Expansion
Designers use the EPM9320LC84-20N to add 60 extra 5-V tolerant I/Os to older microcontrollers that have insufficient native pins, eliminating the need for external I/O expander ICs with limited drive strength. The CPLD's 5-V I/O compatibility matches 8051, PIC, and AVR MCU families directly without level translation, and its high-drive outputs can sink/source 24 mA per pin for LED and relay driving. The in-system programmability via JTAG lets engineers iterate on the I/O map during development. Compared with SPI/I2C I/O expanders, the CPLD provides parallel latency (one clock cycle) instead of serial round-trip delays.
推荐
Telecom Backplane & Bus Arbitration
The EPM9320LC84-20N is used in telecom backplanes to arbitrate multiple bus masters, generate timing strobes, and provide bus-isolation logic between redundant control cards. Its 60 I/Os are sufficient for one full bus-arbitration tree plus status and interrupt fan-out, and the 16 ns tPD meets typical 50 MHz backplane timing budgets with margin. The 5-V tolerance integrates seamlessly with legacy ECL/TTL backplane circuitry, while the JTAG port enables in-field reconfiguration for protocol upgrades. Compared with an FPGA, the CPLD's instant-on (no boot time) and deterministic timing are preferred for hot-swap and failover scenarios.
推荐
推荐产品汇总
工程参考数据： EPM9320LC84-20N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320LI84-20 | EPM9320LI84-10N | EPM9320ALI84-10N |
|---|---|---|---|---|---|---|---|
| Package | PLCC-84 (QCCJ) | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Propagation Delay (tPD) | 16 ns | 15 ns | 10 ns | 16 ns (identical) | 16 ns | 10 ns | 10 ns |
| Internal Frequency | 118 MHz | 125 MHz | 148 MHz | 118 MHz | 118 MHz | 148 MHz | 148 MHz |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 | 60 |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) |
| Lead-Free / RoHS | Yes (N suffix) | Varies by suffix | Varies by suffix | No (leaded) | No (leaded) | Yes (N suffix) | Yes (N suffix) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
关键差异点
- RoHS-compliant lead-free terminal finish （对比 EPM9320LC84-20)
- Drop-in upgrade path to higher speed grades （对比 EPM9320LC84-15)
- Industrial-temperature variant available in same footprint （对比 EPM9320LI84-20)
- 320 macrocells in a single 5-V device vs. lower-density competitors （对比 Generic 5-V CPLD alternatives)
设计说明
The EPM9320LC84-20N requires a stable 5.0 V +/- 5% supply. Place a 0.1 uF ceramic decoupling capacitor as close as possible to each of the four VCC pins (12, 23, 54, 75) and one bulk 10-47 uF tantalum or low-ESR electrolytic capacitor near the package. Multiple VCC/GND pairs reduce ground bounce and improve JTAG programming reliability. According to the manufacturer datasheet, inrush current during JTAG programming peaks at ~150 mA per VCC pin, so power-trace widths should be at least 0.5 mm to avoid IR drop.
The 84-pin PLCC socket should be a low-profile through-hole type with J-bend receptacle to match the LC84 outline. For surface-mount assembly, use a PLCC-84 SMT socket rather than direct soldering - hand rework of direct-soldered PLCC is extremely difficult. Maintain at least 8 mil trace/space for the I/O fan-out and reserve a 2-mm keep-out under the package for thermal relief pads. Group I/O banks together on the PCB to simplify routing, since the MAX 9000 architecture restricts some pin functions to specific bank locations.
Do not confuse the EPM9320LC84-20N (commercial, lead-free) with the EPM9320LC84-20 (commercial, leaded) or the EPM9320LI84-20 (industrial) at procurement - the suffix N and L carry both environmental and temperature-grade implications. Always verify the JTAG chain pinout: TMS, TCK, TDI, TDO must be pulled to known states (typically 10 kohm pull-up on TMS/TCK/TDI) when not in use, or the device may enter unintended test modes at power-up. Finally, ensure your programmer supports the MAX 9000 family - older third-party programmers may require a 'device signature' update to recognize the -20N variant.
The 60 user I/Os on the EPM9320LC84-20N can drive 24 mA per pin at 5 V, making them suitable for direct LED and opto-coupler drive. However, for high-speed signals above 50 MHz, add 22-33 ohm series-termination resistors at the CPLD output to dampen transmission-line reflections. The MAX 9000 output edge rates are ~1-2 ns, so treat all output traces longer than 25 mm as transmission lines. Keep clock and JTAG traces short and away from I/O switching lines to minimize crosstalk into the programming logic.
合规信息
Lead-free per N suffix in part number. RoHS compliance based on Intel/Altera lead-free terminal finish designation; verified by 'N' suffix convention. AEC-Q100 not applicable for CPLD in commercial/industrial use. Halogen-free status not specifically listed in available data - left as unknown per data-authenticity rule.
