ADC3224IRGZ25 - Dual 12-Bit 125MSPS Low-Power ADC | TI
部品番号: ADC3224IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.1 | $291.00 |
| 100 | $25.8 | $2,580.00 |
| 500 | $22.95 | $11,475.00 |
| 1,000 | $20.4 | $20,400.00 |
ADC3224IRGZ25 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog voltage at its input and produces a discrete-time digital code word at its output. The converter is the critical bridge between the analog domain (sensors, RF front-ends, audio, instrumentation) and the digital processing domain (FPGAs, ASICs, DSPs). Within the broader taxonomy, the ADC3224 belongs to the pipelined ADC class, which sits between high-speed flash ADCs and high-resolution sigma-delta ADCs in the speed/resolution trade-off. Pipelined ADCs are favored in communications, IF sampling, multi-channel data acquisition, and portable test equipment because of their ability to digitize tens to hundreds of MHz of analog bandwidth at low per-channel power.
Key features of the ADC3224IRGZ25 include a 1.8 V single supply, SNR of 70.2 dBFS at fIN = 70 MHz, SFDR of 87 dBc at the same input frequency, channel isolation of 105 dB, ultra-low power consumption of 116 mW per channel at 125 MSPS, a Serial LVDS (SLVDS) digital interface, a flexible input clock buffer with divide-by-1, -2, -4 options, internal dither, internal chopper, and multi-chip synchronization support.
Architecturally, the device uses a multi-stage pipelined core with digital error correction, integrated input buffer / SHA, on-chip voltage reference, and an SLVDS serializer for low-EMI digital output. The 105 dB channel isolation enables two independent IF sampling channels to share one chip with minimal crosstalk.
Typical applications include communications base-station IF sampling, multi-carrier software-defined radio receivers, portable battery-powered test and measurement, medical imaging front-ends, and dual-channel industrial data-acquisition systems. The pin-to-pin compatibility with the 14-bit ADC3224 family allows drop-in resolution upgrade or downgrade without PCB rework.
When designing with this ADC, ensure the analog input network and the SLVDS output trace lengths are matched for sub-nyquist operation. Decoupling the 1.8 V AVDD and 1.8 V DVDD rails close to the device is critical, because the 116 mW/channel dissipation scales with sampling rate and input frequency.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives within the ADC3x family, and practical design notes that go beyond the manufacturer datasheet to support engineers at the schematic-to-layout stage.
ドロップイン代替品: ADC3224IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC3224IRGZ25 （同一形状・フットプリント） — 相違点: Package, Resolution, Architecture, Input Type, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
ADC3223IRGZ25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$11.98 / 個
データシートを見る →ADC3224IRGZR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC3224IRGZ25 最大定格＆電気的特性
| Architecture | Pipelined, dual-channel |
| 分解能 | 12 bits |
| Number of Channels | 2 |
| Sample Rate (max) | 125 MSPS |
| Input Type | Differential analog inputs |
| Supply Voltage (AVDD / DVDD) | 1.8 V single supply |
| Power Consumption | 116 mW per channel at 125 MSPS |
| SNR (fIN = 70 MHz) | 70.2 dBFS |
| SFDR (fIN = 70 MHz) | 87 dBc |
| Channel Isolation | 105 dB |
| Digital Interface | Serial LVDS (SLVDS) |
| Input Clock Buffer | Divide-by-1, -2, -4 |
| Internal Features | Internal dither and chopper |
| Multi-Chip Sync | Yes |
| パッケージ | 48-pin VQFN (7x7 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40 C to +85 C (industrial) |
| RoHS ステータス | Compliant |
ADC3224IRGZ25 ピン構成
| ピン 1 | AVSS — Analog ground |
| ピン 2 | AVDD — Analog 1.8 V supply |
| ピン 3 | INAP_A — Channel A positive analog input |
| ピン 4 | INAN_A — Channel A negative analog input |
| ピン 5 | VCM_A — Channel A common-mode voltage |
| ピン 6 | INAP_B — Channel B positive analog input |
| ピン 7 | INAN_B — Channel B negative analog input |
| ピン 8 | VCM_B — Channel B common-mode voltage |
| ピン 9 | CLKP — Positive differential input clock |
| ピン 10 | CLKN — Negative differential input clock |
| ピン 11 | AVSS — Analog ground |
| ピン 12 | AVDD — Analog 1.8 V supply |
| ピン 13 | REFT — Internal reference top (decoupling) |
| ピン 14 | REFB — Internal reference bottom (decoupling) |
| ピン 15 | REFVDD — Internal reference 1.8 V supply |
| ピン 16 | REFGND — Internal reference ground |
| ピン 17 | DVDD — Digital 1.8 V supply |
| ピン 18 | DVSS — Digital ground |
| ピン 19 | SLVDS_P_A — Channel A SLVDS positive output data |
| ピン 20 | SLVDS_N_A — Channel A SLVDS negative output data |
| ピン 21 | SLVDS_P_B — Channel B SLVDS positive output data |
| ピン 22 | SLVDS_N_B — Channel B SLVDS negative output data |
| ピン 23 | CLKDIV_S0 — Clock divider control bit 0 |
| ピン 24 | CLKDIV_S1 — Clock divider control bit 1 |
| ピン 25 | RESETn — Active-low reset |
| ピン 26 | PDN — Active-high power-down |
| ピン 27 | DITH_EN — Internal dither enable |
| ピン 28 | CHOP_EN — Internal chopper enable |
| ピン 29 | SYNCn — Multi-chip synchronization input (active low) |
| ピン 30 | SYNC_OUT — Multi-chip synchronization output |
| ピン 31 | DCS_A — Channel A duty-cycle stabilizer input |
| ピン 32 | DCS_B — Channel B duty-cycle stabilizer input |
| ピン 33 | AVDD — Analog 1.8 V supply |
| ピン 34 | AVSS — Analog ground |
| ピン 35 | TEST1 — Test mode input 1 (tie to DVSS for normal operation) |
| ピン 36 | TEST2 — Test mode input 2 (tie to DVSS for normal operation) |
| ピン 37 | DVDD — Digital 1.8 V supply |
| ピン 38 | DVSS — Digital ground |
| ピン 39 | FSR_OUT — Full-scale range control |
| ピン 40 | FS_ADJ — Full-scale adjust input (decoupling recommended) |
| ピン 41 | RESERVED — Reserved (tie to DVSS) |
| ピン 42 | RESERVED — Reserved (tie to DVSS) |
| ピン 43 | RESERVED — Reserved (tie to DVSS) |
| ピン 44 | RESERVED — Reserved (tie to DVSS) |
| ピン 45 | RESERVED — Reserved (tie to DVSS) |
| ピン 46 | RESERVED — Reserved (tie to DVSS) |
| ピン 47 | AVSS — Analog ground (exposed pad) |
| ピン 48 | AVSS — Analog ground (exposed pad) |
主な用途
ADC3224IRGZ25 の用途: 6 件s: Communications IF Sampling, Multi-Carrier Software-Defined Radio, Portable Test & Measurement Equipment, Medical Imaging Front-Ends, Industrial Data Acquisition Systems, Dual-Channel Signal Intelligence / Wideband Recorder.
Communications IF Sampling
The ADC3224IRGZ25's 125 MSPS sample rate, 70.2 dBFS SNR, and 87 dBc SFDR at fIN = 70 MHz make it ideal for IF-strip digitisation in macro-cell base-station receivers. Placed between the analog IF filter and the FPGA SERDES block, the SLVDS output drives multi-carrier 3G/4G/5G LTE downlink chains with dual diversity channels; the 105 dB channel isolation allows two independent antenna paths on one chip, saving PCB area versus two single-channel ADCs. At 116 mW/channel, the 1.8 V single-rail supply keeps per-board power within the typical 4-6 W envelope for compact RRH modules.
おすすめ
Multi-Carrier Software-Defined Radio
Software-defined radio receivers digitising multiple carriers simultaneously rely on wide dynamic range and high channel isolation. The ADC3224IRGZ25's 12-bit / 125 MSPS pipeline provides ~70 dBFS SNR at 70 MHz IF, sufficient to resolve 64-QAM constellations with margin, while the 105 dB channel-to-channel isolation prevents cross-talk between the two simultaneous spectrum slices. Internal dither and chopper reduce idle tones for SDR front-end flexibility across bandwidths, and multi-chip sync support lets designers scale to 4 or 8 channels by synchronising multiple ADC3224 chips.
おすすめ
Portable Test & Measurement Equipment
The ADC3224IRGZ25 powers handheld oscilloscopes, portable spectrum analysers, and bench-top digitizers where 1.8 V single-supply operation and 116 mW/channel efficiency are critical. The dual-channel pipeline allows simultaneous triggering on two channels, while the internal input clock divider-by-1/-2/-4 simplifies clock-tree design across multiple sample-rate settings. SLVDS digital output reduces board EMI compared with parallel CMOS outputs, helping handhelds meet radiated-emissions compliance without heavy shielding.
おすすめ
Medical Imaging Front-Ends
In ultrasound and portable patient-monitoring systems, the ADC3224IRGZ25 digitises the IF return signal from the receive beam-former while running from a single 1.8 V battery-derived rail. The 70.2 dBFS SNR comfortably captures the dynamic range of the beam-formed signal, while the dual-channel configuration aligns with phased-array transducer pairs. Low power dissipation (116 mW/channel) keeps thermal rise near the patient's skin within acceptable limits for handheld probes and tethered transducers alike.
おすすめ
Industrial Data Acquisition Systems
Multi-channel industrial data-acquisition boards use the ADC3224IRGZ25 to digitise two simultaneous strain-gauge, accelerometer, or vibration sensor outputs at up to 125 MSPS for later FFT-based condition monitoring. The pipelined core and internal dither produce clean spectra at the harmonic frequencies of interest, while the on-chip chopper suppresses idle-channel 1/f noise for DC vibration sensors. Per-channel isolation of 105 dB means two independent sensor inputs (such as an accelerometer and a tachometer) can share one chip without cross-talk.
おすすめ
Dual-Channel Signal Intelligence / Wideband Recorder
Comms-intelligence and bandwidth-recording applications require simultaneously capturing two wideband IF streams and streaming them to FPGA-based storage. The ADC3224IRGZ25 provides 125 MSPS per channel, enabling each channel to capture up to ~62.5 MHz of Nyquist-bandwidth content. The integrated SLVDS serializer keeps FPGA pin count low and EMI low, while the multi-chip synchronization pins let multiple ADC3224 chips share sampling timing for 4-, 8-, or 16-channel wideband recorder stacks in a single chassis.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC3224IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC3223IRGZ25 | ADC3224IRGZR |
|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (7x7 mm) | 48-VQFN (7x7 mm) - same | 48-VQFN (7x7 mm) - same |
| Resolution | 12 bits | 14 bits | 12 bits |
| Sample Rate (max) | 125 MSPS | 125 MSPS | 125 MSPS |
| Number of Channels | 2 | 2 | 2 |
| Digital Interface | Serial LVDS (SLVDS) | Serial LVDS (SLVDS) | Serial LVDS (SLVDS) |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V |
| Internal Dither / Chopper | Yes | Yes | Yes |
| RoHS Status | Compliant | Compliant | Compliant |
主な差別化要因
- Pin-compatible resolution upgrade within the same TI ADC3x family （vs ADC3223IRGZ25)
- Dual-channel 12-bit pipelined core with 105 dB isolation （vs ADC3224IRGZR)
- Integrated multi-chip synchronization pins （vs ADC3224IRGZR)
設計ノート
Estimated: ADC3224IRGZ25 total power at dual-channel 125 MSPS is 116 mW/channel x 2 = 232 mW from a single 1.8 V rail. Decouple the AVDD supply with a 1uF ceramic cap plus a 100 nF cap placed within 5 mm of pins 2, 12, and 33. The REFVDD pin (pin 15) needs its own 100 nF decoupler to keep the internal reference quiet and avoid SNR degradation. If switching regulators feed the 1.8 V rail, add a ferrite bead and >=10 uF of post-filter capacitance to hold switching noise 50 dB below the analog signal of interest.
Route SLVDS output pairs (pins 19-22) as 100-ohm differential microstrip with matched trace lengths across each +/- pair (intra-pair skew <= 5 ps). The differential CLKP/CLKN pair (pins 9-10) should be routed identically with the same via count. Avoid routing these traces through the analog input zone on the same layer; instead, isolate with a ground pour stitch on inner layers. The dual-channel analog inputs INAP_A / INAN_A and INAP_B / INAN_B should match in length within 50 mil to preserve 70 dB channel isolation.
Do not float the unused RESERVED pins (35-46) - all must be tied directly to DVSS for normal operation, otherwise the part may behave unpredictably in production. Apply RESETn high at least 500 ns after both AVDD and DVDD reach 1.8 V before issuing a conversion start. Pulsing RESETn after changing CLKDIV_S0/CLKDIV_S1 divider settings is required to flush the pipeline; without it the first conversion after a rate change may be invalid.
Estimated: For best SNR/SFDR, terminate the analog input network with a 50-ohm back-termination resistor at the source and a 50-ohm diff balun centred on VCM (pin 5 or 8). Avoid putting the ADC3224 directly across wideband signals above 250 MHz without an inter-stage anti-alias filter - the -3 dB bandwidth of the front-end SHA limits the 70 dBFS SNR envelope to roughly 130 MHz. For IF above 100 MHz, plan for a 5th-order Butterworth or elliptical filter between mixer and ADC input.
コンプライアンス情報
RoHS compliant per distributor listings. Industrial temperature grade only (-40 C to +85 C); AEC-Q100 not qualified. For automotive applications use AEC-Q100 qualified alternatives.
