ADS62P25IRGC25 - Dual 12-Bit 125 MSPS ADC, 64-VQFN | Texas Instruments
部品番号: ADS62P25IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $48.2 | $48.20 |
| 10 | $43.85 | $438.50 |
| 100 | $39.4 | $3,940.00 |
| 500 | $35.95 | $17,975.00 |
| 1,000 | $32.5 | $32,500.00 |
ADS62P25IRGC25 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and quantizes them into discrete digital codes. The ADS62P25 sits in the high-speed pipeline ADC family, used when systems require many tens of megasamples per second per channel for communications, imaging, or instrumentation. It belongs to the hypernym hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal IC -> semiconductor. Pipeline ADCs specifically use a switched-capacitor architecture that resolves a few bits per stage across cascaded stages to achieve high sample rates at moderate resolution, which is exactly the architecture used here.
Key features include 12-bit resolution with no missing codes, 125 MSPS maximum sample rate, programmable fine gain up to 6 dB plus a 3.5 dB coarse gain for SNR/SFDR trade-off, 95 dB channel-to-channel crosstalk, and a built-in digital processing block with offset correction and fine gain correction in 0.05 dB steps. Selectable DDR LVDS or parallel CMOS outputs let the same hardware target FPGA-based capture boards or legacy parallel DSP interfaces. The integrated low-jitter clock buffer simplifies board design by relaxing external clock requirements.
Typical applications include multi-carrier GSM/UMTS/LTE base-station receivers, cable-headend digitizers, medical imaging front ends, radar and phased-array IF sampling, and test and measurement instrumentation. The wide input bandwidth and selectable output interfaces make it well suited for both diversity receivers and multi-channel oscilloscope platforms.
When designing with this device, treat the analog input network and clock distribution as a single RF subsystem: use a differential transformer driver, keep the clock path short, and provide adequate decoupling on each supply pin. The dual-channel footprint requires that both inputs be impedance-matched to achieve the rated crosstalk and SFDR. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone.
ドロップイン代替品: ADS62P25IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS62P25IRGC25 （同一形状・フットプリント） — 相違点: Input Type, Package, Output Interface, Architecture, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ADS62P25IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62P23IRGC25
✅ ドロップイン✓ 在庫あり
$18.85 / 個
データシートを見る →ADS62P22IRGC25
✅ ドロップイン✓ 在庫あり
$15.5 / 個
データシートを見る →ADS62P25IRGCR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS62P28IRGC25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$17.5 / 個
データシートを見る →ADS62P25IRGC25 最大定格＆電気的特性
| 分解能 | 12 bit |
| Number of Channels | 2 |
| Maximum Sample Rate | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential analog |
| Output Interface | Parallel CMOS or DDR LVDS (selectable) |
| No Missing Codes | 12-bit (guaranteed) |
| Channel-to-Channel Crosstalk | 95 dB |
| Coarse Gain | 3.5 dB |
| Programmable Fine Gain | up to 6 dB |
| Digital Processing Block | Offset correction, fine gain correction (0.05 dB steps) |
| Clock Input | Integrated low-jitter clock buffer |
| パッケージ | 64-pin VQFN (RGC), 9x9 mm |
| 動作温度範囲 | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADS62P25IRGC25 ピン構成
| ピン 1 | INA_P — Analog input A positive (differential) |
| ピン 2 | INA_N — Analog input A negative (differential) |
| ピン 3 | VCM — Common-mode voltage output for input bias |
| ピン 4 | INB_P — Analog input B positive (differential) |
| ピン 5 | INB_N — Analog input B negative (differential) |
| ピン 6 | CLKP — Differential clock input positive |
| ピン 7 | CLKN — Differential clock input negative |
| ピン 8 | SCLK — Serial interface clock |
| ピン 9 | SDATA — Serial interface data |
| ピン 10 | SEN — Serial interface enable |
| ピン 11 | RESET — Hardware reset (active low) |
| ピン 12 | PDN — Power-down control |
| ピン 13 | MODE — Output mode select (CMOS/LVDS) |
| ピン 14 | NC — Not connected (per datasheet) |
| ピン 15 | D0A — Channel A data output bit 0 (LSB) |
| ピン 16 | D1A — Channel A data output bit 1 |
| ピン 17 | D2A — Channel A data output bit 2 |
| ピン 18 | D3A — Channel A data output bit 3 |
| ピン 19 | D4A — Channel A data output bit 4 |
| ピン 20 | D5A — Channel A data output bit 5 |
| ピン 21 | D6A — Channel A data output bit 6 |
| ピン 22 | D7A — Channel A data output bit 7 |
| ピン 23 | D8A — Channel A data output bit 8 |
| ピン 24 | D9A — Channel A data output bit 9 |
| ピン 25 | D10A — Channel A data output bit 10 |
| ピン 26 | D11A — Channel A data output bit 11 (MSB) |
| ピン 27 | CLKOUTA_P — Channel A output clock positive (LVDS) |
| ピン 28 | CLKOUTA_N — Channel A output clock negative (LVDS) |
| ピン 29 | D0B — Channel B data output bit 0 (LSB) |
| ピン 30 | D1B — Channel B data output bit 1 |
| ピン 31 | D2B — Channel B data output bit 2 |
| ピン 32 | D3B — Channel B data output bit 3 |
| ピン 33 | D4B — Channel B data output bit 4 |
| ピン 34 | D5B — Channel B data output bit 5 |
| ピン 35 | D6B — Channel B data output bit 6 |
| ピン 36 | D7B — Channel B data output bit 7 |
| ピン 37 | D8B — Channel B data output bit 8 |
| ピン 38 | D9B — Channel B data output bit 9 |
| ピン 39 | D10B — Channel B data output bit 10 |
| ピン 40 | D11B — Channel B data output bit 11 (MSB) |
| ピン 41 | CLKOUTB_P — Channel B output clock positive (LVDS) |
| ピン 42 | CLKOUTB_N — Channel B output clock negative (LVDS) |
| ピン 43 | NC — Not connected (per datasheet) |
| ピン 44 | NC — Not connected (per datasheet) |
| ピン 45 | AVDD33 — Analog 3.3V supply |
| ピン 46 | AVDD33 — Analog 3.3V supply |
| ピン 47 | AVDD18 — Analog 1.8V supply |
| ピン 48 | AVDD18 — Analog 1.8V supply |
| ピン 49 | AVDD18 — Analog 1.8V supply |
| ピン 50 | AVDD18 — Analog 1.8V supply |
| ピン 51 | DRVDD — Digital output driver supply |
| ピン 52 | DRVDD — Digital output driver supply |
| ピン 53 | DVDD — Digital 1.8V supply |
| ピン 54 | DVDD — Digital 1.8V supply |
| ピン 55 | DVDD — Digital 1.8V supply |
| ピン 56 | NC — Not connected (per datasheet) |
| ピン 57 | NC — Not connected (per datasheet) |
| ピン 58 | NC — Not connected (per datasheet) |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | NC — Not connected (per datasheet) |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | NC — Not connected (per datasheet) |
主な用途
ADS62P25IRGC25 の用途: 6 件s: Multi-Carrier Wireless Base Station Receiver, Cable Headend Digitizer, Medical Ultrasound Beamformer Front End, Wideband Radar and Phased-Array IF Sampling, Test and Measurement Instrumentation, Software Defined Radio (SDR) Receiver.
Multi-Carrier Wireless Base Station Receiver
The ADS62P25IRGC25 is well matched to multi-carrier GSM/UMTS/LTE base-station receivers where two diversity channels must be digitized simultaneously. Its dual 12-bit channels at 125 MSPS comfortably handle wideband IF signals, and the 95 dB channel-to-channel crosstalk preserves isolation between diversity branches. The selectable DDR LVDS output pairs directly with FPGAs from Xilinx Altera, simplifying timing closure at high sample rates. Per the TI ADS62P25 datasheet, the integrated low-jitter clock buffer relaxes clock-tree design while still delivering the SNR/SFDR required by 3G/4G receiver chains. The 64-VQFN (RGC) footprint keeps the analog front-end compact enough to fit behind the antenna feed network on a typical remote-radio-head PCB.
おすすめ
Cable Headend Digitizer
Cable-headend equipment digitizes upstream and downstream QAM carriers at IF, and the ADS62P25IRGC25 is a strong fit because its 125 MSPS rate captures several adjacent carriers per channel. The 12-bit resolution and no-missing-codes guarantee preserve modulation error ratio (MER) under real-world cable impairments, while the 95 dB crosstalk keeps dual upstream paths isolated. Designers can use the parallel CMOS output mode to drive legacy QAM demodulator ASICs, or DDR LVDS for modern FPGA-based demodulation. Per TI datasheet guidance, the differential analog inputs accept the typical IF transformer network used in cable downstream receivers without external buffer amplifiers.
おすすめ
Medical Ultrasound Beamformer Front End
Ultrasound beamformer front ends require many simultaneous low-noise ADC channels, and the ADS62P25IRGC25 is well suited because its dual-channel 12-bit architecture reduces PCB area in dense probe arrays. The 125 MSPS rate covers the 40 MHz IF bandwidth typical of premium ultrasound probes, while the digital offset and fine gain correction blocks compensate for channel-to-channel analog mismatches. Per the TI ADS62P25 datasheet, the LVDS output simplifies routing across the dozens of channels feeding the beamformer FPGA. The industrial -40C to +85C temperature range also supports portable cart-based systems that see wider thermal swings than a fixed clinical room.
おすすめ
Wideband Radar and Phased-Array IF Sampling
Phased-array radar systems digitize multiple IF channels in parallel and need ADCs with tightly matched gain and phase. The ADS62P25IRGC25 delivers dual 12-bit 125 MSPS channels in one package, which keeps the analog signal path short and matched for accurate beamforming. The selectable DDR LVDS output and low-jitter integrated clock buffer preserve the timing relationships critical to angle-of-arrival accuracy. Per TI, the digital processing block with fine gain correction in 0.05 dB steps enables precise per-channel calibration. The VQFN-64 footprint is small enough to fit behind each radiating element's T/R module in high-density electronically steered arrays.
おすすめ
Test and Measurement Instrumentation
Bench oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers use ADCs like the ADS62P25IRGC25 to capture wideband repetitive and transient signals. The 125 MSPS sample rate captures signals well above the audio band, while the dual channels handle differential probes or two simultaneous time bases. The programmable fine gain up to 6 dB lets designers trade SNR against SFDR depending on whether they emphasize noise floor or harmonic distortion in measurement results. Per the TI ADS62P25 datasheet, the LVDS CMOS-selectable interface supports both modern FPGA-based scopes and legacy parallel-bus instruments without redesigning the analog front end.
おすすめ
Software Defined Radio (SDR) Receiver
Software defined radio platforms rely on wideband ADC front ends to push as much signal chain as possible into the digital domain, and the ADS62P25IRGC25 fits this role well. Two independent 12-bit 125 MSPS channels capture I/Q signal pairs from a single RF mixer with closely matched gain and phase. The DDR LVDS output streams up to several Gbps of data into an FPGA for digital downconversion and channelization. Per TI, the integrated low-jitter clock buffer simplifies the LO-to-ADC clock distribution and preserves SNR across the full Nyquist bandwidth. Designers benefit from a single 64-VQFN device replacing two single-channel ADCs in space-constrained SDR modules.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS62P25IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS62P25IRGCT | ADS62P23IRGC25 | ADS62P22IRGC25 | ADS62P25IRGCR | ADS62P28IRGC25 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Maximum Sample Rate | 125 MSPS | 125 MSPS | 80 MSPS | 65 MSPS | 125 MSPS | 105 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Output Interface | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Highest sample rate in the ADS62P2X 12-bit family （vs ADS62P23IRGC25 (80 MSPS))
- Dual-channel integration reduces PCB area versus two single-channel ADCs （vs Two discrete 12-bit single-channel ADCs)
- Selectable DDR LVDS or CMOS output in one device （vs ADS62P22IRGC25 (65 MSPS variant))
設計ノート
The ADS62P25IRGC25 requires careful PCB layout to achieve rated SFDR. Place a continuous ground plane on layer 2 beneath the analog input traces, keep input traces matched in length and width, and use a transformer-coupled differential input network on INA_P/INA_N and INB_P/INB_N. Per the TI ADS62P25 datasheet, the exposed thermal pad must be soldered to a low-impedance ground pour with multiple stitching vias for thermal dissipation.
Decouple each AVDD33, AVDD18, DVDD, and DRVDD pin with a 0.1uF ceramic capacitor placed within 2 mm of the pin, plus a 10uF bulk capacitor per supply rail. Use a ferrite bead or pi-filter to isolate the analog 3.3V supply from the digital 3.3V supply if both rails share an upstream LDO. Per TI, inadequate decoupling is the most common cause of degraded SNR and SFDR on the ADS62P2X family.
Route the differential clock input (CLKP/CLKN) with controlled 100-ohm differential impedance and keep it away from switching digital outputs. The integrated low-jitter clock buffer accepts a wide range of clock amplitudes, but a clean sinusoidal or LVPECL driver is recommended for best jitter performance. Per TI, the clock path should be treated as an RF signal and not as a digital control line.
Do not exceed the absolute maximum analog input voltage on INA or INB pins; the integrated ESD diodes are sensitive to over-voltage events at power-up before the analog supply rail settles. Sequence AVDD33 first, then AVDD18/DVDD, and only after both rails are stable should the clock and analog input be applied. Per the TI ADS62P25 datasheet, failure to sequence supplies can permanently damage the device.
コンプライアンス情報
RoHS compliance confirmed via TI product page. Industrial temperature grade -40C to +85C. AEC-Q100 not applicable since this is an industrial-grade ADC; automotive versions would be specified differently.
