Intel

EP1SGX25DF672C6N - Stratix GX FPGA, 25K LE, 672-FBGA | Intel (Altera)

部品番号: EP1SGX25DF672C6N ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1.5 V Vdss FBGA-672 (FC-FBGA), 33 x 33 mm, 1.0 mm pitch Package

開始価格 $210 USD / 個

MOQ: 1 |

価格更新日: 2026-09-07

ボリューム価格

数量	単価	小計
1	$285	$285.00
10	$265.5	$2,655.00
100	$245.75	$24,575.00
500	$228	$114,000.00
1,000	$210	$210,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP1SGX25DF672C6N 概要

The Intel (formerly Altera) EP1SGX25DF672C6N is a high-density Stratix GX family Field Programmable Gate Array (FPGA) integrating 25,660 logic elements (cells) in a 672-ball Fine-pitch Ball Grid Array (FC-FBGA / FBGA-672) measuring 33 x 33 mm with 1.0 mm ball pitch. It is fabricated on a 130 nm CMOS process, operates from a 1.5 V core supply, and is rated for the commercial 0C to 85C operating range.

An FPGA (Field-Programmable Gate Array) is a programmable semiconductor whose logic fabric, block RAM, DSP blocks, and I/O can be reconfigured after manufacture, allowing engineers to implement arbitrary digital logic, signal-processing pipelines, and high-speed serial interfaces without a custom ASIC. Stratix GX sits within Intel's high-performance FPGA hierarchy as a transceiver-equipped variant of the original Stratix family, optimized for communication, video, and signal-processing designs. This places the EP1SGX25DF672C6N at the high-performance end of the programmable-logic taxonomy: FPGA > programmable logic > semiconductor IC.

Key features include 2,566 LABs (Logic Array Blocks), 455 user I/O pins, embedded transceiver channels for high-speed serial connectivity, distributed and block RAM, dedicated DSP blocks for multiplication-intensive pipelines, and on-chip PLLs for clock generation and management. The 1.0 mm-pitch FBGA-672 package supports the high I/O count and transceiver signal-integrity requirements typical of line-card and backplane designs.

Typical applications include telecom line cards, broadband aggregation equipment, high-speed serial protocol bridging (e.g., custom SERDES-based links), video and image processing pipelines, and military/aerospace signal-processing subsystems. The 1.5 V core combined with multi-gigabit transceivers makes this part especially attractive where deterministic latency and high throughput are required.

When designing with this device, plan PCB stack-up, decoupling, and power sequencing carefully because 672-ball BGAs demand matched-length routing, abundant ground vias, and a multi-rail power network. The Altera (now Intel FPGA) Quartus II design suite supports this family natively, with reference designs, IP cores, and transceiver toolkits accelerating integration.

This page synthesizes distributor pricing, in-family drop-in alternatives, and practical design notes beyond what is repeated in the manufacturer datasheet, giving the engineer a faster procurement and design-validation path.

ドロップイン代替品: EP1SGX25DF672C6N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP1SGX25DF672C6N （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Process Technology, Speed Grade, Number of Transceivers.

EP1SGX25CF672C5

Altera

Operating Temperature: 0°C to +85°C (Commercial)

Process Technology: 0.13 µm CMOS

Number of Transceivers: 12

比較対象 EP1SGX25DF672C6N →

EP1SGX25CF672C6N

Intel

Operating Temperature: 0 °C to +85 °C

Package: 672-ball FBGA (FineLine BGA)

Speed Grade: -6 (commercial)

比較対象 EP1SGX25DF672C6N →

EP1SGX25CF672C7N

Altera

Operating Temperature: 0 C to 85 C (Commercial)

Package: 672-ball FC-FBGA

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672C5N

Intel

Operating Temperature: 0 C to 85 C (Commercial)

Speed Grade: C5

Number of Transceivers: 20

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672C6

Intel

Operating Temperature: 0C to +85C (commercial)

Package: 672-BBGA FineLine BGA

Process Technology: CMOS

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672C7

Intel

Operating Temperature: 0 °C to +85 °C (Commercial)

Package: 672-FBGA (27 × 27 mm, 1.0 mm pitch)

Process Technology: 0.13 µm CMOS, SRAM-based

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672C7ES

Intel

Operating Temperature: 0 °C to 85 °C

Package: 672-pin FC-FBGA

Process Technology: 130 nm

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672C7N

Intel

Operating Temperature: 0 °C to 85 °C (Commercial)

Package: 672-ball FineLine BGA (FBGA-672)

Speed Grade: C7

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672I5N

Intel

Operating Temperature: -40C to +85C (Industrial)

Package: 672-ball FC-FBGA

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF672I6

Intel

Operating Temperature: -40C to +85C (industrial, I6 grade)

Package: 672-BBGA (FC-FBGA), 33 x 33 mm, 1.0 mm pitch

比較対象 EP1SGX25DF672C6N →

EP1SGX25DF800C5N

Intel

Operating Temperature: 0C to +85C (commercial)

Package: FBGA-800 (FineLine BGA, 31x31 mm)

✅ ドロップイン

Altera

📦 FBGA-672

Stratix® GX · Stratix I GX · 25,660 · 2,566 · 1,944,576 · 455 · 12 · 14 (18x18)

✓ 在庫あり

$1304.99 / 個

データシートを見る →

EP1SGX25DF672C6N 最大定格＆電気的特性

Series	Stratix GX
Family	Stratix GX (Stratix I GX)
Logic Elements / Cells	25,660
Logic Array Blocks (LABs)	2,566
User I/O Count	455
Core Supply Voltage	1.5 V
Process Technology	130 nm CMOS
Logic Family	CMOS
パッケージ	FBGA-672 (FC-FBGA), 33 x 33 mm, 1.0 mm pitch
動作温度	0C to 85C (commercial)
実装タイプ	Surface Mount
MSLレベル	3 (168 hours)
HTSUS Code	8542.39.0001
RoHS ステータス	Lead Free (per part suffix 'N' designator)
ピン数	672

EP1SGX25DF672C6N ピン構成

ピン A1	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file for ball-specific function (FBGA-672 multi-function pins)
ピン B1	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A2	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B2	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A3	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B3	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A4	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B4	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A5	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B5	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A6	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B6	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A7	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B7	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A8	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B8	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A9	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B9	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン A10	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file
ピン B10	I/O / GND / VCC — User I/O, power, or ground - refer to Quartus II pinout file

主な用途

EP1SGX25DF672C6N の用途: 6 件s: Telecom Line Card Aggregation, High-Speed Serial Protocol Bridging, Video and Image Processing Pipelines, Military and Aerospace Signal Processing, Industrial Control and Test Equipment, Legacy Replacement and Long-Life Maintenance.

🌐

Telecom Line Card Aggregation

The EP1SGX25DF672C6N's 25,660 logic elements and integrated high-speed transceiver channels make it well suited for telecom line-card aggregation, where multiple SERDES lanes must be bonded, packetized, and forwarded to a framer. With 455 user I/Os, designers can connect parallel SFI buses, tributary framers, and control-plane microcontrollers without external bridging logic. Its 1.5 V core combined with 130 nm CMOS process delivers deterministic latency required for telecom timing budgets. Quartus II IP cores support POS-PHY, SPI-4.2, and UTOPIA interfaces out of the box, accelerating time to market for legacy and next-gen line cards.

おすすめ

🔧

High-Speed Serial Protocol Bridging

Stratix GX transceivers let the EP1SGX25DF672C6N bridge between proprietary SERDES rates and standard protocols such as PCIe, XAUI, or custom backplane links. The 25K logic cell budget absorbs protocol stacks, link-training state machines, and DMA controllers on a single die, eliminating the need for a companion protocol ASIC. The FBGA-672 package with 1.0 mm pitch provides the controlled-impedance environment required for multi-gigabit signal integrity. Designers can use Quartus II's Transceiver Toolkit to characterize eye diagrams and tune pre-emphasis on a per-channel basis.

おすすめ

EP1SGX40F1020C7N (Higher-density family member for richer protocol stacks) EP1SGX25DF672C5N · Intel

📺

Video and Image Processing Pipelines

With 2,566 LABs and dedicated DSP blocks, the EP1SGX25DF672C6N implements real-time video scaling, deinterlacing, and color-space conversion pipelines for broadcast and surveillance equipment. The 455 user I/Os accept parallel BT.1120, DVI, or LVDS video streams and drive multi-format HDMI/DVI output stages without external bus switches. The 1.5 V core keeps power within a manageable envelope for fan-cooled video appliances, while the 0C-85C operating range supports standard commercial chassis. Reference designs from Altera provide head-start IP for SDI, DisplayPort, and HD-SDI transport.

おすすめ

EP1S25F672C7N · Altera EP1SGX25CF672C7N · Altera

✈️

Military and Aerospace Signal Processing

Although the EP1SGX25DF672C6N is commercial-grade (0C-85C), its high logic density and SERDES resources are commonly used as the development platform for ruggedized signal-processing subsystems that later transition to industrial-temperature Stratix GX parts. The FBGA-672 package supports controlled-impedance routing required by radar, EW, and SIGINT signal chains. Designers prototype the digital front-end on commercial parts and migrate to EP1SGX25 variants with industrial or military temperature grades once the architecture stabilizes, preserving Quartus II project compatibility across the swap.

おすすめ

EP1SGX25CF672I6N · Intel EP1S40F1020I6N · Intel

🏭

Industrial Control and Test Equipment

Programmable-logic test platforms for industrial control use the EP1SGX25DF672C6N's 25K LEs to host custom stimulus generators, protocol emulators, and high-speed digitizer interfaces on a single FPGA. The 455 I/Os accept parallel ADC/DAC buses, isolated GPIO, and encoder feedback channels used in motor control and precision test. Quartus II's SignalTap logic analyzer embedded in the silicon allows non-intrusive debug during burn-in, eliminating the need for external logic analyzers in production test racks. The 1.5 V core plus PLLs simplifies multi-clock-domain timing for mixed-rate industrial protocols.

おすすめ

EP1S25F672C6N · Intel EP1SGX10CF672C7N · Intel

🖥️

Legacy Replacement and Long-Life Maintenance

Because the EP1SGX25DF672C6N is obsolete, long-life programs in medical, industrial, and transportation infrastructure often must keep equivalent parts available for repair and spare-pool replenishment. Verified drop-in alternates such as EP1SGX25DF672C5N, EP1SGX25CF672C7N, and EP1SGX25CF672C6N share the FBGA-672 footprint, allowing qualified re-work on existing boards. Field engineers can re-spin service stock by sourcing the same Quartus II bitstream across these variants, provided the timing closure is re-validated. This protects multi-decade service commitments on deployed equipment.

おすすめ

EP1SGX25CF672C6N · Intel EP1SGX25DF672C5N · Intel

おすすめ製品の概要

EP1SGX25CF672C7N Altera 使用用途: Telecom Line Card Aggregation, Video and Image Processing Pipelines EP1SGX10DF672C6N Altera 使用用途: Telecom Line Card Aggregation EP1SGX40F1020C7N Higher-density family member for richer protocol stacks 使用用途: High-Speed Serial Protocol Bridging EP1SGX25DF672C5N Intel 使用用途: High-Speed Serial Protocol Bridging, Legacy Replacement and Long-Life Maintenance EP1S25F672C7N Altera 使用用途: Video and Image Processing Pipelines EP1SGX25CF672I6N Intel 使用用途: Military and Aerospace Signal Processing EP1S40F1020I6N Intel 使用用途: Military and Aerospace Signal Processing EP1S25F672C6N Intel 使用用途: Industrial Control and Test Equipment EP1SGX10CF672C7N Intel 使用用途: Industrial Control and Test Equipment EP1SGX25CF672C6N Intel 使用用途: Legacy Replacement and Long-Life Maintenance

What is the EP1SGX25DF672C6N?

The EP1SGX25DF672C6N is an Intel (formerly Altera) Stratix GX family FPGA with 25,660 logic elements and 455 user I/Os, housed in a 672-ball FC-FBGA package. According to the Stratix GX Device Family Data Sheet, it operates from a 1.5 V core supply and is fabricated on a 130 nm CMOS process for high-performance logic and transceiver designs.

What package does the EP1SGX25DF672C6N use?

The EP1SGX25DF672C6N is packaged in a 672-ball Fine-pitch Flip-Chip BGA (FC-FBGA) measuring 33 x 33 mm with 1.0 mm ball pitch. This large BGA supports the device's high I/O count and high-speed transceiver channels while providing the thermal mass required for 130 nm FPGA operation.

How many logic elements and LABs does this FPGA have?

The EP1SGX25DF672C6N contains 25,660 logic elements (LEs/cells) organized into 2,566 Logic Array Blocks (LABs), with embedded block RAM, DSP blocks, and PLL clock resources. According to the Stratix GX datasheet, this places it in the mid-to-high density tier of the original Stratix GX product line, suitable for telecom line-card designs.

Is the EP1SGX25DF672C6N still in production?

The EP1SGX25DF672C6N is obsolete and no longer in active production by Intel. As of 2026-09-07, only limited distributor stock and refurbished parts are available through brokers such as Sierra IC, Kynix, Ariat-Tech, and Element HK, with pricing reflecting scarcity rather than OEM channels.

Where can I buy EP1SGX25DF672C6N online?

As of 2026-09-07, the EP1SGX25DF672C6N can be sourced from independent distributors and brokers including DigiKey, Mouser, Arrow, Sierra IC, Kynix, Ariat-Tech, Element HK, and Xecor. Because the part is obsolete, buyers should validate date codes, lot traceability, and supplier certifications before committing to volume orders.

What is the price of EP1SGX25DF672C6N?

Pricing for the EP1SGX25DF672C6N as of 2026-09-07 ranges roughly from $210 to $285 USD per unit depending on quantity tier, with single-piece pricing near $285 and volume breaks around $210 at 1,000 pieces. Obsolete FPGA pricing is volatile; always request a fresh quote, as broker inventory and OEM last-time-buy stock shift weekly.

What is the lead time for EP1SGX25DF672C6N?

Lead time for the obsolete EP1SGX25DF672C6N typically ranges from 2 to 8 weeks depending on supplier and lot size, as of 2026-09-07. Independent brokers draw from broker inventory, factory surplus, and refurbished stock, so buyers should confirm delivery dates in writing before releasing purchase orders for production builds.

EP1SGX25DF672C6N vs EP1SGX25DF672C6 - what is the difference?

The trailing 'N' suffix in EP1SGX25DF672C6N denotes a lead-free, RoHS-compliant terminal finish, while the bare EP1SGX25DF672C6 (without 'N') typically ships with a SnPb (leaded) finish. Per Intel (Altera) ordering code conventions, the parts share the same die and package but differ only in lead-free status for environmental compliance.

What is the best drop-in replacement for EP1SGX25DF672C6N?

The closest drop-in replacements are other 672-ball FBGA Stratix GX 25K-family devices with the same speed grade and pinout, such as EP1SGX25CF672C7N, EP1SGX25CF672C6N, or EP1SGX25DF672C5N. According to Stratix GX datasheet pinout maps, these parts share the FBGA-672 ball map and only differ in speed grade or commercial/industrial qualification, enabling direct substitution.

Can EP1SGX25CF672C6N replace EP1SGX25DF672C6N?

Yes, the EP1SGX25CF672C6N is an in-family Stratix GX 25K part in the same FBGA-672 package and can serve as a drop-in substitute for EP1SGX25DF672C6N in most designs. According to Stratix GX ordering information, the 'C' suffix denotes a different speed grade than the original 'D' part, so designers should re-validate timing closure in Quartus II before committing.

What design software supports EP1SGX25DF672C6N?

The EP1SGX25DF672C6N is supported by Altera Quartus II design software, including the Quartus II Web Edition (free) and Subscription Edition. According to Intel FPGA documentation, Quartus II provides device support files, IP cores, and the TimeQuest timing analyzer needed to compile and verify Stratix GX designs targeting this device.

Where to download EP1SGX25DF672C6N datasheet PDF?

The official Stratix GX Device Family Data Sheet is hosted on the Intel FPGA documentation portal at intel.com under the Stratix literature hub. Search for the Stratix GX (Stratix I GX) Device Family Data Sheet, which covers EP1SGX25DF672C6N device specifications, pinout, and DC characteristics in a single PDF volume.

Where to find EP1SGX25DF672C6N pinout?

The EP1SGX25DF672C6N pinout is documented in the Stratix GX Device Family Data Sheet, specifically the Pin Information chapter and the device-specific addendum that maps all 672 FBGA balls to bank assignments, transceiver channels, and dedicated configuration pins. Quartus II's Pin Planner tool also generates a project-specific pin-out report for the device.

Is EP1SGX25DF672C6N RoHS compliant?

Yes, the 'N' suffix in EP1SGX25DF672C6N indicates a lead-free, RoHS-compliant terminal finish per Altera (Intel FPGA) ordering conventions. Designers targeting non-RoHS markets should instead select the non-N variant EP1SGX25DF672C6, which uses a conventional SnPb finish but is otherwise identical.

What are the key specifications of EP1SGX25DF672C6N that engineers should know?

Key EP1SGX25DF672C6N specifications are: 25,660 logic elements, 2,566 LABs, 455 user I/Os, 1.5 V core supply, 130 nm CMOS process, FBGA-672 package at 33 x 33 mm with 1.0 mm pitch, and 0C-85C commercial operating range. According to the Stratix GX datasheet, this combination targets telecom, video, and high-speed serial designs.

エンジニアリング参考データ: EP1SGX25DF672C6N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP1SGX25DF672C6N when you need a mid-to-high-density Stratix GX FPGA with 25,660 LEs, 455 user I/Os, and integrated high-speed transceivers in a 672-ball FBGA for telecom line cards, video pipelines, or SERDES-based protocol bridges in commercial temperature applications. Select EP1SGX25DF672C5N if you can tolerate a slightly slower speed grade and want to optimize cost, or EP1SGX25CF672C7N if you need the fastest C7 grade for higher line rates. For non-RoHS legacy lines, use EP1SGX25DF672C6 instead of the 1-N variant. For lower-density designs, choose EP1SGX10 variants; for industrial temperature, step up to EP1SGX25CF672I6N. All options share the FBGA-672 footprint and Quartus II tool flow.

代替品との比較

パラメータ	この製品	EP1SGX25DF672C6	EP1SGX25DF672C5N	EP1SGX25CF672C7N	EP1SGX25CF672C6N	EP1SGX25CF672C5
Brand	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)
Package	FBGA-672 (33x33 mm, 1.0 mm pitch)	FBGA-672 (same)	FBGA-672 (same)	FBGA-672 (same)	FBGA-672 (same)	FBGA-672 (same)
Logic Elements	25,660	25,660	25,660	25,660	25,660	25,660
User I/O Count	455	455	455	455	455	455
Speed Grade	C6	C6	C5 (slower)	C7 (faster)	C6	C5 (slower)
Core Supply Voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
RoHS / Lead-Free	Yes (lead-free, 'N' suffix)	No (SnPb finish)	Yes	Yes	Yes	No (SnPb finish)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

主な差別化要因

Drop-in interchangeable with full family （vs EP1SGX25DF672C5N)
Higher-density Stratix GX 25K variant for richer pipelines （vs EP1SGX10DF672C6N)
Lead-free RoHS variant of the same die （vs EP1SGX25DF672C6)

設計ノート

FBGA-672 at 1.0 mm pitch requires a 4-to-6 layer PCB stack-up with matched-length differential routing and a continuous ground reference plane beneath every transceiver lane. Place 0.1 uF X7R decoupling capacitors within 2 mm of every VCC ball, with bulk 10-22 uF tantalum or polymer capacitors on each power rail. Route all high-speed SERDES lanes on the top microstrip layer with no more than two vias per TX/RX pair, and stitch ground vias along the lane edges to suppress return-path discontinuities.

Although the 130 nm Stratix GX FPGA is not the highest-power device in its class, a fully populated 25K-LE design with all transceivers active can dissipate 5-8 W. The FC-FBGA-672 package relies on the PCB top-side copper pour and forced airflow for cooling. Provide at least 4 cm^2 of contiguous top copper under the BGA, thermal vias to inner ground planes (0.3 mm drill, 0.6 mm pitch), and a low-velocity (~1 m/s) heatsink or fan in enclosed chassis to keep junction temperature below 100C.

Do not assume pin compatibility with the smaller FBGA-484 or FBGA-1020 Stratix GX parts; the FBGA-672 ball map is unique to this package and the 672-ball family. When migrating to EP1SGX25DF1020 variants, expect a complete BGA re-ball, pin remapping, and Quartus II device re-assignment. Also verify that all configuration pins (MSEL, nCE, nCONFIG, DATA, DCLK) are pulled correctly during power-up - misconfigured MSEL pins are a common cause of silent configuration failure on first prototypes.

コンプライアンス情報

RoHS

Compliant

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Yes

ハロゲンフリー

Unknown

紛争鉱物

Unknown

Lead-free per 'N' suffix; HTSUS 8542.39.0001 confirmed by DigChip listing. REACH, halogen-free, and conflict-minerals declarations not explicitly provided in verified web data.

データ検証日: 2026-09-07 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

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