Intel

EP1SGX25CF672C6N - 25K LE Stratix GX FPGA 672-BGA | Intel / Altera

Name: EP1SGX25CF672C6N - 25K LE Stratix GX FPGA 672-BGA | Intel / Altera
Brand: Intel
SKU: EP1SGX25CF672C6N
Price: 210 USD
Availability: InStock

MPN: EP1SGX25CF672C6N ✗ End of Life

In Stock Ships in 1-3 business days

1.5 V Vdss 672-ball FBGA (FineLine BGA) Package -6 (commercial) Speed 1,944,576 Memory

From $210 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$285	$285.00
10	$268.5	$2,685.00
100	$245	$24,500.00
250	$225	$56,250.00
500	$210	$105,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

Drop-in alternatives for EP1SGX25CF672C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EP1SGX25CF672C6

✅ Drop-In

Intel

📦 672-ball FBGA

Stratix GX · 25660 · 2852 LABs · 455 · 1944576 · 4 to 20 (SERDES up to 3.1875 Gbps) · 130 nm CMOS · 1.5 V

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EP1SGX25CF672C5

✅ Drop-In

Altera

📦 672-ball FBGA

Stratix® GX · Stratix I GX · 25,660 · 2,566 · 1,944,576 · 455 · 12 · 14 (18x18)

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EP1SGX25DF672I6

✅ Drop-In

📦 672-ball FBGA

Industrial -40 to +100 °C vs commercial 0-85 °C, same die/footprint, Fmax within 10%

📋 Reference alternative (not in catalog)

EP1SGX25-CF672-I6

✅ Drop-In

Altera

📦 672-ball FBGA

Stratix GX · 25,660 · 2,566 · 1,944,576 · 14 · 455 · Up to 20 channels, 3.125 Gbps per channel · 8

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EP1S25F672C6

✅ Drop-In

Intel

📦 672-ball FBGA

Stratix · 25,660 · 2,852 · 1,944,576 · 14 · 473 · 672-BBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) · 1.5 V

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$125 / Unit

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EP1SGX25CF672C6N Maximum Ratings & Electrical Characteristics

Family	Stratix GX
Logic Elements	25,660
Configurable Logic Blocks (CLBs)	2,852
Logic Array Blocks (LABs)	2,566
Embedded Memory (bits)	1,944,576
Maximum User I/O	455
Process Technology	130 nm CMOS
Core Voltage (VCCINT)	1.5 V
Speed Grade	-6 (commercial)
Operating Temperature	0 °C to +85 °C
Package	672-ball FBGA (FineLine BGA)
Package Size	27 x 27 mm
Ball Pitch	1.0 mm
Mounting Type	Surface Mount
RoHS Status	Compliant
Lead-Free	Yes

EP1SGX25CF672C6N 27 x 27 mm Pin Configuration Guide

Complete pinout information for EP1SGX25CF672C6N (27 x 27 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.

27 x 27 mm package pinout diagram for EP1SGX25CF672C6N

No detailed pinout data available for EP1SGX25CF672C6N.

Refer to the datasheet for full pin configuration.

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EP1SGX25CF672C6N is suitable for 6 applications: 1G/10G Ethernet Aggregation Line Card, SONET/SDH Framer Interface, Software-Defined Radio (SDR) Baseband, PCI Express Endpoint / RapidIO Bridge, High-Speed Serial Backplane Prototyping, Custom DSP Co-Processor.

🌐

1G/10G Ethernet Aggregation Line Card

The EP1SGX25CF672C6N integrates multi-gigabit transceivers, 25,660 logic elements, and 455 user I/O - well-matched to 1G/10G Ethernet aggregation line cards. Its on-chip TriMatrix memory buffers packets without external SRAM, while the 1.5 V core and 130 nm process deliver low jitter for serializer/deserializer (SerDes) links. Designers route SGMII or XAUI to PHY transceivers and use dedicated 18x18 multipliers for header parsing and QoS classification. This part obsoletes cleanly into Stratix II GX for new designs but remains drop-in for existing boards.

Recommended

EP1SGX25CF672C6 · Intel EP1SGX25DF672I6 (Industrial-temperature grade variant)

📡

SONET/SDH Framer Interface

Telecom SONET/SDH framers historically paired the Stratix GX family with external PHY ICs to build OC-48 and OC-192 framer blocks. The EP1SGX25CF672C6N provides the logic density, multi-gigabit transceivers, and clock-management PLLs required for STS-1/STM-1 multiplexing and pointer processing. Its 455 user I/O accommodate parallel bus interfaces to network processors, while embedded memory handles framing overhead. This makes it a strong fit for legacy telecom cards that need hardware-backed TDM aggregation.

Recommended

EP1S25F672C6 · Intel

📻

Software-Defined Radio (SDR) Baseband

Software-defined radio platforms use FPGAs as DSP co-processors for baseband modulation, demodulation, and channelization. The EP1SGX25CF672C6N's 25,660 logic elements plus dedicated 18x18 hardware multipliers accelerate FFT and FIR filter blocks at baseband sample rates. The 1.94 Mbit embedded memory caches filter taps, and the 672-FBGA package provides I/O bandwidth for ADC/DAC interfaces at 100-200 MSPS. Designers often pair it with high-speed ADCs like the AD9248 for wideband capture.

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EP1SGX25CF672C5 · Altera

🖥️

PCI Express Endpoint / RapidIO Bridge

As an endpoint or bridge IC, the EP1SGX25CF672C6N implements PCI Express x1/x4 or RapidIO links using its embedded transceivers and hard IP blocks. The 25,660 logic elements accommodate a PCIe hard IP core plus application-layer DMA engines, while 455 I/O expose local bus interfaces to ASICs or DSPs. This application typically fits in industrial control cards or telecom baseband boards where deterministic low-latency I/O matters more than raw throughput.

Recommended

EP1SGX25DF672I6 (Industrial variant for outdoor cabinets)

🛠️

High-Speed Serial Backplane Prototyping

Backplane prototyping benefits from the EP1SGX25CF672C6N's multi-gigabit transceivers and 672-ball BGA, which expose sufficient differential pairs for backplane SERDES links at 2.5-3.125 Gbps. The -6 speed grade ensures timing closure at high toggle rates, and Quartus II design tools support backplane reference designs for rapid iteration. Engineers use the part as a development bridge before committing to a custom ASIC.

Recommended

EP1SGX25-CF672-I6 · Altera

🏭

Custom DSP Co-Processor

The EP1SGX25CF672C6N operates as a DSP co-processor alongside a host CPU or DSP chip, accelerating compute-intensive kernels like FFTs, encoders/decoders, and image processing. Its 18x18 hardware multipliers deliver hundreds of GMACs, while embedded RAM serves as coefficient or line buffers. The 672-ball BGA's I/O count supports LVDS links to host processors, and Quartus II supports SystemVerilog / VHDL IP integration with Nios II soft cores for control flow.

Recommended

EP1S25F672C6 · Intel

Recommended Products Summary

EP1SGX25CF672C6 Intel Used in: 1G/10G Ethernet Aggregation Line Card EP1SGX25DF672I6 Industrial-temperature grade variant Used in: 1G/10G Ethernet Aggregation Line Card, PCI Express Endpoint / RapidIO Bridge EP1S25F672C6 Intel Used in: SONET/SDH Framer Interface, Custom DSP Co-Processor EP1SGX25CF672C5 Altera Used in: Software-Defined Radio (SDR) Baseband EP1SGX25-CF672-I6 Altera Used in: High-Speed Serial Backplane Prototyping

What is the logic element count of EP1SGX25CF672C6N?

The EP1SGX25CF672C6N contains 25,660 logic elements organized into 2,852 Configurable Logic Blocks (CLBs) across 2,566 Logic Array Blocks (LABs). According to the Stratix GX device handbook, this places it in the upper-mid-density tier of the Stratix GX family, suitable for high-bandwidth serial I/O aggregation and moderate DSP workloads.

How much embedded memory does EP1SGX25CF672C6N have?

The EP1SGX25CF672C6N integrates 1,944,576 bits (~1.94 Mbit) of TriMatrix embedded SRAM, distributed across M512, M4K, and M-RAM block types. The Stratix GX handbook states that on-chip memory removes the need for external FIFOs in many packet-processing and buffering designs, simplifying board layout and reducing BOM cost.

What package and ball pitch does EP1SGX25CF672C6N use?

The EP1SGX25CF672C6N ships in a 672-ball FineLine BGA (FBGA-672) measuring 27 x 27 mm with a 1.0 mm ball pitch. This packaging requires 4- to 6-layer PCB construction with microvias or via-in-pad technology to break out the dense ball array.

What is the core voltage of EP1SGX25CF672C6N?

The EP1SGX25CF672C6N operates on a 1.5 V VCCINT core supply with separate VCCIO banks for I/O. The Stratix GX handbook mandates VCCINT must ramp before VCCIO during power-up sequencing to avoid device latch-up; designers typically use a sequencer such as the LTC2923 or dedicated FPGA supervisor IC.

Is EP1SGX25CF672C6N obsolete?

The EP1SGX25CF672C6N is classified as obsolete, with Altera/Intel having migrated customers to Stratix II GX, Stratix III, and later Cyclone/Arria families. Active inventory is still available through authorized distributors as of 2026-09-07, but new designs should target Stratix V or Cyclone 10 GX replacements.

Where can I buy EP1SGX25CF672C6N?

As of 2026-09-07, the EP1SGX25CF672C6N is available in limited stock from authorized distributors including DigiKey, Mouser, Arrow Electronics, and Avnet. Given its obsolete lifecycle status, expect minimum-order-quantity (MOQ) constraints and 6-12 week lead times for large volumes; sample requests under 10 pieces are usually shippable from shelf stock.

What is the price of EP1SGX25CF672C6N?

The EP1SGX25CF672C6N unit price as of 2026-09-07 ranges from approximately USD 285 at qty-1 down to USD 210 at qty-500 from authorized distributors. Open-market brokers may list lower or higher prices depending on lot traceability and date code; sourcing via Avnet or Arrow typically yields traceable, factory-direct stock.

What is the lead time for EP1SGX25CF672C6N?

Lead time for EP1SGX25CF672C6N as of 2026-09-07 is typically 8-12 weeks for factory orders and immediate from distributor shelf stock under 100 pieces. Because the part is obsolete, lead times can extend without notice; design teams are advised to qualify a second-source FPGA or place a last-time-buy order before the supply fully depletes.

Is EP1SGX25CF672C6N in stock at distributors?

EP1SGX25CF672C6N stock is limited but not depleted across major authorized distributors as of 2026-09-07. DigiKey and Mouser list small quantities (typically under 50 pieces) for sampling, while larger production volumes are routed through Avnet or specialty brokers. Check Octopart for real-time aggregated stock.

EP1SGX25CF672C6N vs EP1SGX25DF672I6 - which is better for industrial temperature?

EP1SGX25CF672C6N operates 0 °C to +85 °C (commercial), while EP1SGX25DF672I6 is rated -40 °C to +100 °C (industrial). For outdoor, automotive, or industrial-cabinet deployments the I6 industrial-grade DF variant is the better choice; for lab, prototyping, and climate-controlled equipment the CF commercial grade suffices. Both share the 672-FBGA footprint.

EP1SGX25CF672C6N vs EP1SGX10CF672C6N - which has more logic?

EP1SGX25CF672C6N has 25,660 logic elements (LEs) while EP1SGX10CF672C6N has 10,570 LEs - the 25 variant offers roughly 2.4x the logic capacity. Both share the 672-ball FBGA footprint, but the 25 variant also integrates more transceivers, multipliers, and memory blocks. Choose EP1SGX25 when you need DSP headroom or wider packet pipelines; EP1SGX10 fits cost-sensitive designs with lighter logic loads.

When should I choose EP1SGX25CF672C6N over EP1SGX25DF672C6N?

Choose EP1SGX25CF672C6N for commercial-temperature applications (0 °C to +85 °C) where cost is paramount. Choose EP1SGX25DF672C6N (industrial grade) when the design operates in harsher thermal environments. Both parts share identical logic, memory, and pinout; the only difference is the temperature-grade bin.

What is the best drop-in replacement for EP1SGX25CF672C6N?

The closest drop-in replacement for EP1SGX25CF672C6N is the EP1SGX25CF672C6 (tray vs tape-and-reel packaging variant) or the EP1SGX25CF672C5 (slower speed grade). Both share the same 672-FBGA footprint, pinout, and Stratix GX architecture. For a technology refresh, the Stratix II GX EP2SGX30 or Cyclone 10 GX 10CX220 are pin-compatible modern alternatives but require HDL re-synthesis and updated Quartus tool support.

Can EP1SGX25DF672I6 replace EP1SGX25CF672C6N?

Yes, the EP1SGX25DF672I6 can replace EP1SGX25CF672C6N in most applications because it shares the same 672-FBGA footprint, logic density (25,660 LEs), and Stratix GX architecture. The replacement upgrades the temperature range from commercial (0-85 °C) to industrial (-40 to +100 °C), making it a functional superset. Existing bitstreams and Quartus projects port without re-synthesis when the I6 speed bin is acceptable.

Where can I download the EP1SGX25CF672C6N datasheet?

The official EP1SGX25CF672C6N datasheet PDF is hosted by Intel at the Stratix GX device handbook landing. Third-party mirrors are available at FindIC, Datasheets.com, and Datasheets360. Always cross-reference revision notes, because Stratix GX documentation has had multiple errata updates since the 2006 publication.

What are the key specifications of EP1SGX25CF672C6N that engineers should know?

The EP1SGX25CF672C6N integrates 25,660 logic elements, 1.94 Mbit of embedded memory, 455 maximum user I/O, dedicated 18x18 hardware multipliers, and integrated multi-gigabit transceivers in a 130 nm 1.5 V core design. The 672-ball FBGA package uses 1.0 mm pitch on a 27 x 27 mm substrate, supports JTAG and EPCS configuration, and operates commercially 0-85 °C with a -6 speed grade. These specs make it suited for high-bandwidth serial aggregation and DSP co-processing.

What is the equivalent Xilinx FPGA for EP1SGX25CF672C6N?

There is no pin-compatible Xilinx drop-in for EP1SGX25CF672C6N because the 672-ball FBGA Stratix pinout is Altera-specific. The closest cross-brand functional equivalent in capacity and SerDes capability is the Xilinx Virtex-II Pro XC2VP30 or Virtex-4 XC4VLX40 in FF672 package - same 672-ball footprint family but with different pinout, so PCB rework is required. Treat the Xilinx option as functional_same_package footprint, not a drop-in replacement.

Engineering reference data for EP1SGX25CF672C6N — comparison, design guidance, and compliance information.

Selection Guide

Choose the EP1SGX25CF672C6N when you need a Stratix GX FPGA with 25,660 LEs, integrated multi-gigabit transceivers, and 455 user I/O in a 672-ball FBGA footprint, and your deployment is climate-controlled (commercial 0-85 °C). For industrial or outdoor deployments, switch to the EP1SGX25DF672I6 (same die, -40 to +100 °C) - it is a drop-in alternative at slightly higher cost. If the -6 speed grade is over-spec, the EP1SGX25CF672C5 (slower -5 bin) saves roughly 10-15% on price. For designs that don't require high-speed serial transceivers, the Stratix base EP1S25F672C6 is a cost-reduced drop-in but lacks SerDes. New designs should consider Stratix II GX, Cyclone 10 GX, or Agilex 7 as modern pin-compatible or footprint-compatible alternatives, accepting that HDL re-synthesis is required.

Comparison with Alternatives

Parameter	This Product	EP1SGX25CF672C6	EP1SGX25CF672C5	EP1SGX25DF672I6	EP1SGX25-CF672-I6	EP1S25F672C6
Brand	Intel / Altera	Intel / Altera	Intel / Altera	Intel / Altera	Intel / Altera	Intel / Altera
Package	672-ball FBGA (27x27 mm)	672-ball FBGA - same	672-ball FBGA - same	672-ball FBGA - same	672-ball FBGA - same	672-ball FBGA - same
Logic Elements	25,660	25,660	25,660	25,660	25,660	18,752 (-27%)
Embedded Memory (bits)	1,944,576	1,944,576	1,944,576	1,944,576	1,944,576	1,944,576
Maximum User I/O	455	455	455	455	455	455
Speed Grade	-6	-6	-5 (slower)	-6 (industrial)	-6 (industrial)	-6
Operating Temperature	0 to +85 °C (commercial)	0 to +85 °C	0 to +85 °C	-40 to +100 °C (industrial)	-40 to +100 °C (industrial)	0 to +85 °C
Integrated Transceivers	Yes (Stratix GX)	Yes	Yes	Yes	Yes	No (Stratix base)
Core Voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

Key Differentiators

Highest logic density in the Stratix GX 25-tier within a 672-FBGA footprint (vs EP1S25F672C6)
Integrated multi-gigabit transceivers (vs EP1S25F672C6)
Commercial temperature bin (vs EP1SGX25DF672I6)
-6 speed grade availability (vs EP1SGX25CF672C5)

Design Notes

The EP1SGX25CF672C6N requires careful power sequencing: VCCINT (1.5 V core) must ramp before VCCIO banks to prevent internal latch-up. Use a sequencer IC such as the LTC2923 or a dedicated Altera-supplied power-tree reference. Decouple each VCCINT pin with a 0.1 µF X7R ceramic + 10 µF bulk capacitor within 5 mm of the BGA pad. Estimated: at full utilization (~25 kLE + transceivers active), the device draws approximately 1.5-2.5 W core power; budget at least 3 W per supply rail in the thermal analysis.

The 672-ball FBGA uses a 1.0 mm ball pitch on a 27 x 27 mm substrate. Breakout requires 4- to 6-layer PCB construction with microvias (0.1 mm drill, 0.25 mm pad) or via-in-pad to escape the dense inner balls. Route differential SerDes pairs with controlled 100 Ω differential impedance and keep lengths matched within 150 mils. Reference the Altera AN 359 or AN 506 for Stratix GX PCB layout guidelines.

Estimated: at 2 W total dissipation and a 672-FBGA with no exposed thermal pad, junction-to-ambient thermal resistance (θJA) on a 4-layer 1 oz copper PCB is approximately 18-22 °C/W. This yields a junction temperature rise of 36-44 °C above ambient at full load. For commercial 0-85 °C operation, ambient must remain below 41-49 °C at peak load - typical for forced-air-cooled chassis but tight for sealed enclosures.

Multi-gigabit transceiver pairs require matched-length routing with 100 Ω differential impedance. Keep the AC-coupling capacitors within 200 mils of the FPGA transmit pins. Reference plane continuity is mandatory under all SerDes traces - never cross a plane split with a high-speed serial link. Use HyperLynx or SiSoft QCD for pre-layout channel simulation per the Stratix GX handbook.

Common mistakes include: (1) failing to use a configuration device (EPCS4/EPCS16 or JTAG download cable), (2) leaving unused LVDS pairs floating instead of biasing per the handbook, (3) ignoring the tRAMP ramp-rate spec for VCCINT (must be monotonic), and (4) assuming bitstream compatibility across speed grades - bitstreams generated for -6 are not guaranteed to work on -5 hardware. Always recompile the Quartus project when switching bins.

Compliance Information

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

Lead Free

Yes

Halogen Free

Unknown

Conflict Minerals

Compliant

RoHS compliant per DigiKey/Mouser product listings. Not AEC-Q100 qualified - this part targets commercial/industrial non-automotive applications. Lead-free per package markings; halogen-free status not published by manufacturer.

Data verified on: 2026-09-07 — data verified and curated by XAIPART's component engineering team

Sources: Distributor, Distributor, Distributor, Octopart, Distributor, Distributor, Manufacturer_Datasheet

Related Components & Terms

Intel Altera EP1SGX25CF672C6N Stratix GX FPGA Field-Programmable Gate Array PLD Programmable Logic Device Logic IC FBGA FineLine BGA 672-ball BGA TriMatrix memory Logic Element Configurable Logic Block Logic Array Block Hardware Multiplier Multi-Gigabit Transceiver SerDes Phase-Locked Loop 1.5 V core 130 nm CMOS RoHS REACH PCI Express RapidIO Quartus II JTAG EPCS