EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
部品番号: EPM9560RC208-15N ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $19.85 | $19,850.00 |
EPM9560RC208-15N 概要
A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that sits between small SPLDs/PLDs and large FPGAs in the programmable logic taxonomy (SPLD -> CPLD -> FPGA -> programmable logic -> semiconductor). CPLDs are characterized by deterministic timing (predictable, fixed propagation delays), low static power consumption, and flash/EEPROM-based configuration that retains the bitstream without an external boot memory, making them ideal for glue logic, bus interfacing, power-up sequencing, and high-speed control planes. The MAX architecture arranges macrocells in Logic Array Blocks (LABs) interconnected by a programmable switch matrix called the Programmable Interconnect Array (PIA), giving the EPM9560 family its signature combination of high I/O count and predictable timing.
Key features of the EPM9560RC208-15N include 560 macrocells, 212 user I/O pins (in this 208-RQFP variant), a 15 ns tPD (pin-to-pin delay), 117.6 MHz maximum internal frequency, 5.0 V core operation, and JTAG/IEEE 1149.1 boundary-scan test support. The device is offered in a 208-pin Power Quad Flat Pack (RQFP/BQFP) package suitable for socketed or surface-mount legacy designs, with pin counts up to 304 available in the broader MAX 9560 family.
Architecturally, the EPM9560RC208-15N uses EEPROM configuration memory to retain the user logic across power cycles, removing the need for an external configuration PROM. Its deterministic timing model simplifies worst-case static timing analysis in safety-critical and industrial control applications. The 5.0-V tolerant I/O is directly compatible with TTL and CMOS logic families widely used in legacy industrial designs, telecom infrastructure, and military/aerospace subsystems.
Typical applications for the EPM9560RC208-15N include high-speed address decoding and bus interfacing, glue logic for microprocessor/DSP systems, peripheral controllers in industrial automation, telecom backplane bridging, and legacy ASIC/small-FPGA replacement. The 15 ns speed grade suits designs where predictable sub-20 ns timing closure is required without the complexity and boot time of an FPGA.
When designing with this device, confirm that your tool flow targets the legacy MAX+PLUS II or Quartus MAX 9000 device support library; the bitstream is incompatible with newer MAX II/MAX V CPLDs. JTAG programming via the ByteBlasterMV or USB-Blaster download cable is recommended for production programming. Note that the MAX 9000 family is mature/EOL - design for long-life-cycle availability before committing to a new design.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer product page alone.
ドロップイン代替品: EPM9560RC208-15N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC208-15N （同一形状・フットプリント） — 相違点: Package, Speed Grade, User I/O Pins, In-System Programmability, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC208-15
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-10N
✅ ドロップイン✓ 在庫あり
$175 / 個
データシートを見る →EPM9560ARC208-10N
✅ ドロップイン✓ 在庫あり
$27.2 / 個
データシートを見る →EPM9560RC208-15C
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-14
✅ ドロップイン✓ 在庫あり
$27.9 / 個
データシートを見る →EPM9560RC208-13
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-15N 最大定格＆電気的特性
| Series | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| User I/O | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Maximum Internal Frequency | 117.6 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | CMOS EEPROM (non-volatile) |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature (commercial) | 0C to +70C |
| 実装タイプ | Surface Mount |
| Speed Grade | -15 (15 ns tPD) |
| Architecture | Multiple Array MatriX (MAX) - third generation |
EPM9560RC208-15N ピン構成
| ピン 1 | I/O — User I/O pin (signal assigned via Quartus/MAX+PLUS II pin planner) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | I/O — User I/O pin |
| ピン 15 | I/O — User I/O pin |
| ピン 16 | I/O — User I/O pin |
| ピン 17 | I/O — User I/O pin |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | I/O — User I/O pin |
| ピン 22 | I/O — User I/O pin |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | I/O — User I/O pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | I/O — User I/O pin |
| ピン 42 | I/O — User I/O pin |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | I/O — User I/O pin |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | I/O — User I/O pin |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | I/O — User I/O pin |
| ピン 85 | I/O — User I/O pin |
| ピン 86 | I/O — User I/O pin |
| ピン 87 | I/O — User I/O pin |
| ピン 88 | I/O — User I/O pin |
| ピン 89 | I/O — User I/O pin |
| ピン 90 | I/O — User I/O pin |
| ピン 91 | I/O — User I/O pin |
| ピン 92 | I/O — User I/O pin |
| ピン 93 | I/O — User I/O pin |
| ピン 94 | I/O — User I/O pin |
| ピン 95 | I/O — User I/O pin |
| ピン 96 | I/O — User I/O pin |
| ピン 97 | I/O — User I/O pin |
| ピン 98 | I/O — User I/O pin |
| ピン 99 | I/O — User I/O pin |
| ピン 100 | I/O — User I/O pin |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin |
| ピン 103 | I/O — User I/O pin |
| ピン 104 | I/O — User I/O pin |
| ピン 105 | I/O — User I/O pin |
| ピン 106 | I/O — User I/O pin |
| ピン 107 | I/O — User I/O pin |
| ピン 108 | I/O — User I/O pin |
| ピン 109 | I/O — User I/O pin |
| ピン 110 | I/O — User I/O pin |
| ピン 111 | I/O — User I/O pin |
| ピン 112 | I/O — User I/O pin |
| ピン 113 | I/O — User I/O pin |
| ピン 114 | I/O — User I/O pin |
| ピン 115 | I/O — User I/O pin |
| ピン 116 | I/O — User I/O pin |
| ピン 117 | I/O — User I/O pin |
| ピン 118 | I/O — User I/O pin |
| ピン 119 | I/O — User I/O pin |
| ピン 120 | I/O — User I/O pin |
| ピン 121 | I/O — User I/O pin |
| ピン 122 | I/O — User I/O pin |
| ピン 123 | I/O — User I/O pin |
| ピン 124 | I/O — User I/O pin |
| ピン 125 | I/O — User I/O pin |
| ピン 126 | GND — Ground |
| ピン 127 | I/O — User I/O pin |
| ピン 128 | I/O — User I/O pin |
| ピン 129 | I/O — User I/O pin |
| ピン 130 | I/O — User I/O pin |
| ピン 131 | I/O — User I/O pin |
| ピン 132 | I/O — User I/O pin |
| ピン 133 | I/O — User I/O pin |
| ピン 134 | I/O — User I/O pin |
| ピン 135 | I/O — User I/O pin |
| ピン 136 | I/O — User I/O pin |
| ピン 137 | I/O — User I/O pin |
| ピン 138 | I/O — User I/O pin |
| ピン 139 | I/O — User I/O pin |
| ピン 140 | I/O — User I/O pin |
| ピン 141 | I/O — User I/O pin |
| ピン 142 | I/O — User I/O pin |
| ピン 143 | I/O — User I/O pin |
| ピン 144 | I/O — User I/O pin |
| ピン 145 | I/O — User I/O pin |
| ピン 146 | I/O — User I/O pin |
| ピン 147 | I/O — User I/O pin |
| ピン 148 | I/O — User I/O pin |
| ピン 149 | I/O — User I/O pin |
| ピン 150 | I/O — User I/O pin |
| ピン 151 | I/O — User I/O pin |
| ピン 152 | GND — Ground |
| ピン 153 | I/O — User I/O pin |
| ピン 154 | I/O — User I/O pin |
| ピン 155 | I/O — User I/O pin |
| ピン 156 | I/O — User I/O pin |
| ピン 157 | I/O — User I/O pin |
| ピン 158 | I/O — User I/O pin |
| ピン 159 | I/O — User I/O pin |
| ピン 160 | I/O — User I/O pin |
| ピン 161 | I/O — User I/O pin |
| ピン 162 | I/O — User I/O pin |
| ピン 163 | I/O — User I/O pin |
| ピン 164 | I/O — User I/O pin |
| ピン 165 | I/O — User I/O pin |
| ピン 166 | I/O — User I/O pin |
| ピン 167 | I/O — User I/O pin |
| ピン 168 | I/O — User I/O pin |
| ピン 169 | I/O — User I/O pin |
| ピン 170 | I/O — User I/O pin |
| ピン 171 | I/O — User I/O pin |
| ピン 172 | I/O — User I/O pin |
| ピン 173 | I/O — User I/O pin |
| ピン 174 | I/O — User I/O pin |
| ピン 175 | I/O — User I/O pin |
| ピン 176 | I/O — User I/O pin |
| ピン 177 | I/O — User I/O pin |
| ピン 178 | I/O — User I/O pin |
| ピン 179 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 180 | TMS — JTAG Test Mode Select |
| ピン 181 | TCK — JTAG Test Clock |
| ピン 182 | TDO — JTAG Test Data Out |
| ピン 183 | GND — Ground |
| ピン 184 | VCC — 5.0 V Core Supply |
| ピン 185 | I/O — User I/O pin |
| ピン 186 | I/O — User I/O pin |
| ピン 187 | I/O — User I/O pin |
| ピン 188 | I/O — User I/O pin |
| ピン 189 | I/O — User I/O pin |
| ピン 190 | I/O — User I/O pin |
| ピン 191 | I/O — User I/O pin |
| ピン 192 | I/O — User I/O pin |
| ピン 193 | I/O — User I/O pin |
| ピン 194 | I/O — User I/O pin |
| ピン 195 | I/O — User I/O pin |
| ピン 196 | I/O — User I/O pin |
| ピン 197 | I/O — User I/O pin |
| ピン 198 | I/O — User I/O pin |
| ピン 199 | I/O — User I/O pin |
| ピン 200 | I/O — User I/O pin |
| ピン 201 | I/O — User I/O pin |
| ピン 202 | I/O — User I/O pin |
| ピン 203 | I/O — User I/O pin |
| ピン 204 | GND — Ground |
| ピン 205 | I/O — User I/O pin |
| ピン 206 | I/O — User I/O pin |
| ピン 207 | I/O — User I/O pin |
| ピン 208 | I/O — User I/O pin |
主な用途
EPM9560RC208-15N の用途: 6 件s: High-Speed Address Decoding and Bus Interfacing, Industrial Automation and Process Control, Telecom Backplane Bridging and Protocol Conversion, Legacy ASIC and Small-FPGA Replacement, Power-Up Sequencing and Reset Distribution, Military and Aerospace Legacy Avionics.
High-Speed Address Decoding and Bus Interfacing
The EPM9560RC208-15N's 15 ns pin-to-pin delay and 560 macrocells make it ideal for high-speed address decoding and bus-interfacing glue logic in microprocessor and DSP systems. With 212 user I/O pins in the 208-RQFP variant, the device can decode large memory address spaces and generate chip-select signals for multiple peripherals in parallel - for example, generating 8 chip-selects from a 24-bit address bus within a single clock cycle. Its deterministic timing model lets engineers close timing without false paths, which is critical in industrial control planes where the CPLD sits between a 50-80 MHz host CPU and legacy 5 V peripherals.
おすすめ
Industrial Automation and Process Control
In industrial automation and process control, the EPM9560RC208-15N serves as a deterministic logic controller for PLC backplanes, sensor aggregation, and motor-driver interfacing. Its 5.0 V I/O directly interfaces with 5 V industrial logic, removing the need for level shifters in 24 V PLC I/O modules. The 560-macrocell capacity is sufficient to implement complex state machines for conveyor sequencing, PID loop control, or safety interlocks. The EEPROM-based configuration retains the bitstream across power cycles, enabling instant-on behavior that is critical in factory-floor shutdown/recovery scenarios.
おすすめ
Telecom Backplane Bridging and Protocol Conversion
The EPM9560RC208-15N is widely used in telecom backplanes for protocol bridging between legacy TDM buses (H.110, MVIP, SCSA) and newer packet-based fabrics. Its 15 ns tPD and 117.6 MHz internal frequency support sub-20 ns serial-to-parallel conversion and back, while the 212 I/O pins handle the wide parallel buses typical of telecom line cards. The JTAG/IEEE 1149.1 boundary-scan interface simplifies in-system test of high-density backplane assemblies. Because MAX 9000 CPLDs have been deployed in telecom infrastructure for 20+ years, the -15N is a known-quantity part for long-life-cycle designs.
おすすめ
Legacy ASIC and Small-FPGA Replacement
The EPM9560RC208-15N is a popular drop-in replacement for obsolete ASICs and small FPGAs in long-life military, aerospace, and industrial programs. Its 208-RQFP package matches many 1990s-era ASIC footprints, allowing board-level redesign without changing the PCB. The non-volatile EEPROM configuration eliminates the boot PROM and configuration supervisor required by SRAM-based FPGAs, reducing BOM count and improving MTBF. Designers can convert legacy ASIC netlists to MAX+PLUS II HDL or schematic capture, then synthesize into the 560 macrocells to extend product life without re-spinning the board.
おすすめ
Power-Up Sequencing and Reset Distribution
The EPM9560RC208-15N is ideal for power-up sequencing and reset distribution in multi-rail systems where multiple voltage domains must come up in a specific order to prevent latch-up. Its 5.0 V core and I/O can directly interface with supervisory reset generators, and its deterministic timing ensures precise rail-to-rail sequencing delays. The 560 macrocells comfortably implement 8-16 sequencing channels with watchdog timers and brown-out detection logic. Because the configuration is non-volatile EEPROM, the sequencing logic is active the instant power is applied - critical for FPGAs and ASICs that need a clean reset before their configuration memory loads.
おすすめ
Military and Aerospace Legacy Avionics
The EPM9560RC208-15N is specified for military temperature ranges and is widely deployed in legacy avionics subsystems, radar signal processing backplanes, and weapons-system controllers. Its 560-macrocell density supports the complex state machines and bus arbiters required in MIL-STD-1553, ARINC 429, and other avionics data buses. The 208-RQFP package is compatible with the through-hole and socketed assembly methods common in military hardware. While the commercial-grade -15N variant (0C to +70C) is the most available, extended-temperature variants exist within the broader MAX 9560 family for harsh-environment applications.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC208-15N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC208-15 | EPM9560RC208-10N | EPM9560ARC208-10N | EPM9560RC208-15C | EPM9560RC208-14 | EPM9560RC208-13 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 208-RQFP | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns | 10 ns (33% faster) | 10 ns (33% faster) | 15 ns | 14 ns | 13 ns |
| Maximum Internal Frequency | 117.6 MHz | 117.6 MHz | 125 MHz | 125 MHz | 117.6 MHz | 125 MHz | 125 MHz |
| Core Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Memory | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM |
| JTAG (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy |
主な差別化要因
- Standard mainstream speed grade with best availability （vs EPM9560RC208-10N)
- Lead-free / RoHS-compliant N-suffix finish （vs EPM9560RC208-15)
- 208-pin RQFP footprint compatible across entire MAX 9560 family （vs EPM9560RC240-15)
設計ノート
The EPM9560RC208-15N draws Icc from a single 5.0 V rail; consult the MAX 9000 datasheet DC characteristics for Icc vs frequency and vs output switching loading. Estimated: with 50% I/O toggling at 50 MHz into 50 pF loads, expect ICC in the 200-400 mA range. Provide at least four 0.1 uF decoupling capacitors placed adjacent to VCC/GND pin pairs around the 208-RQFP perimeter, plus a bulk 10-47 uF tantalum or ceramic capacitor at the supply entry point. Add a bulk reservoir to handle simultaneous-output-switching (SSO) current spikes that can exceed 1 A on densely-switching outputs.
The 208-RQFP package has 0.5 mm pin pitch with gull-wing leads on all four sides - use a 4-layer PCB with continuous ground and power planes to minimize ground bounce and SSO noise. Estimated: keep all signal traces shorter than 50 mm to avoid transmission-line effects above 50 MHz, and use 33 ohm series termination on clock outputs driving more than 25 mm of trace. Provide a solid ground plane directly under the device to reduce EMI; the RQFP package's exposed leads make excellent thermal vias when stitched to inner ground planes.
The MAX 9000 family is in last-time-buy status, so design for long-term obsolescence before committing to a new production design. Common pitfalls include: (1) using MAX+PLUS II instead of Quartus - both are supported but Quartus MAX 9000 device support requires the legacy device library installation; (2) assuming signal-soft or buffered feature compatibility with MAX 7000 - register all I/O configurations explicitly in the project; (3) forgetting the JTAG TCK pull-down and TMS pull-up resistors required for reliable in-system programming; (4) mating a -15N design with an -10N footprint without re-running static timing analysis.
Place JTAG pins TDI, TMS, TCK, and TDO on accessible board test points or a 2x5 pin header for in-system programming via ByteBlasterMV or USB-Blaster. Estimated: route JTAG signals with the same 50 mm trace-length guideline as other high-speed signals to avoid programming failures. Add a JTAG chain-include resistor network if multiple JTAG devices share the bus, and document the JTAG chain order in the design files. For production programming, the IEEE 1149.1 boundary-scan interface also enables in-circuit test (ICT) for bed-of-nails fixtures.
コンプライアンス情報
RoHS/REACH/lead-free status depends on the specific part marking and date code. The -N suffix generally indicates lead-free/RoHS-compliant finish for newer manufacturing lots, but always verify against the Certificate of Conformance (CoC) from your franchised distributor. MAX 9000 family is not AEC-Q100 qualified - automotive applications require separate qualification.