EP20K600CF672I9N - APEX 20KC 600K FPGA, 672-FBGA, Industrial | Intel
부품 번호: EP20K600CF672I9N ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $145 | $14,500.00 |
| 500 | $130 | $65,000.00 |
| 1,000 | $120 | $120,000.00 |
EP20K600CF672I9N 개요
The APEX 20KC family is an SRAM-based programmable logic device (PLD) combining look-up table (LUT) logic with embedded array blocks (EABs), positioning it between classic CPLDs and modern FPGAs. As a member of the broader FPGA -> programmable logic -> logic IC -> integrated circuit taxonomy, the APEX 20KC series was engineered for high-volume, performance-oriented designs where integration of memory and logic reduces system chip count and PCB complexity.
Key features include 24,320 logic cells, 311,040 typical gates, 312 Kbits of embedded memory, multi-standard I/O support (LVTTL, LVCMOS, PCI, SSTL, GTL+), and up to four phase-locked loops (PLLs) for clock management. The device supports in-system programmability via the IEEE 1149.1 JTAG interface and configuration via serial or parallel EPROMs, allowing rapid prototyping and field upgrades without removing the device from the board.
Architecturally, the APEX 20KC combines an enhanced MultiCore architecture with a hierarchical interconnect, providing predictable timing and high utilization across large designs. The LUT-based logic elements operate in conjunction with embedded array blocks (EABs) that can be configured as RAM, ROM, or product-term logic, giving designers a flexible mix of fine-grain and coarse-grain resources.
Typical applications include telecommunications line cards, network switches, video processing pipelines, DSP co-processors, and industrial automation controllers. The 600K-gate density makes it suitable for data-path-heavy designs such as protocol bridges and packet classifiers, while the integrated PLLs and high-speed I/O support serializer/deserializer (SERDES) interfaces in legacy telecom systems.
When designing with the EP20K600CF672I9N, engineers should pay close attention to power-supply sequencing (1.8 V VCCINT must rise before or coincident with VCCIO), proper JTAG chain termination, and adequate thermal dissipation through the FC-FBGA thermal pad. Because this is a legacy APEX 20KC device, long-term availability may be limited; consult Intel's product longevity report for current lifecycle status before committing to new designs.
This page consolidates distributor pricing, verified specifications, drop-in alternatives from the APEX 20K family, and practical design notes that go beyond what is summarized in the manufacturer datasheet.
드롭인 대체품: EP20K600CF672I9N — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K600CF672I9N (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Package, Process Technology, Device Type, Core Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K600CF672I8N
✅ 드롭인✓ 재고 있음
$138 / 개
데이터시트 보기 →EP20K600CF672I7N
✅ 드롭인✓ 재고 있음
$232 / 개
데이터시트 보기 →EP20K600CF672C9N
✅ 드롭인✓ 재고 있음
$175 / 개
데이터시트 보기 →EP20K600CF672C8N
✅ 드롭인✓ 재고 있음
$108 / 개
데이터시트 보기 →EP20K600CF672C7N
✅ 드롭인✓ 재고 있음
$108 / 개
데이터시트 보기 →EP20K600CB652C8N
✅ 드롭인✓ 재고 있음
$115 / 개
데이터시트 보기 →EP20K600CF672I9N 최대 정격 & 전기적 특성
| Family | APEX 20KC |
| Logic Elements | 24,320 cells |
| Typical Gates | 600,000 |
| Maximum Frequency | 250 MHz |
| Process Technology | 0.15 µm CMOS |
| Core Voltage (VCCINT) | 1.8 V |
| Embedded Memory | 311,040 bits (approx. 38 KB) |
| 패키지 | 672-ball FC-FBGA |
| Configuration Mode | JTAG / Serial / Parallel |
| Programming Interface | IEEE 1149.1 JTAG |
| 동작 온도 | -40 °C to +85 °C (industrial) |
EP20K600CF672I9N 672-ball fc-fbga 핀 구성 가이드
EP20K600CF672I9N(672-ball fc-fbga 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP20K600CF672I9N.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP20K600CF672I9N 적합 용도: 7 애플리케이션s: Telecommunications Line Cards, Network Switches and Routers, Video Processing Pipelines, DSP Co-Processors and Accelerators, Industrial Automation Controllers, Legacy Protocol Bridges and Bus Converters, Test and Measurement Instrumentation.
Telecommunications Line Cards
The EP20K600CF672I9N's 24,320 logic cells and 600K-gate density fit legacy telecom line cards that integrate framer, MAC, and traffic-management functions on a single FPGA. Its 250 MHz internal performance and embedded array blocks (EABs) provide on-chip buffering for cell/packet queues, while the 1.8 V core reduces power versus older 2.5 V APEX 20K designs. Industrial temperature grading (-40 C to +85 C) is required for central-office and outdoor-cabinet deployments. Place the device between the TDM/SerDes framer and the network processor, using the embedded PLLs to derive multiple clock domains for STS/STM payload rates.
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Network Switches and Routers
In enterprise and carrier-grade switches, the EP20K600CF672I9N handles table lookup, queue management, and packet-classification functions. The 311 Kbits of embedded memory can be configured as CAM for MAC/address tables or as FIFO buffers for back-pressure flow control. Multi-standard I/O support (LVTTL, LVCMOS, GTL+) interfaces directly to switch-fabric ASICs and PHY devices without external level translation. The 672-ball FC-FBGA package provides the signal-integrity and pin-density required for 32-bit+ data paths running at 100 MHz and above.
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Video Processing Pipelines
The EP20K600CF672I9N is well-suited to multi-standard video processing, including MPEG-2/H.264 pre-processing, scaling, and de-interlacing. Its high logic-cell count enables parallel pixel pipelines that meet 1080p60 throughput, while the EABs implement line buffers and lookup tables for color-space conversion. The 1.8 V core keeps power dissipation manageable in fan-less set-top boxes and video-wall controllers. JTAG-based configuration allows post-production firmware updates without removing the device from the field.
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DSP Co-Processors and Accelerators
Pair the EP20K600CF672I9N with a host DSP or microprocessor to offload compute-intensive kernels such as FFT, FIR filtering, or Reed-Solomon encoding. The LUT-based logic elements implement bit-level parallelism far more efficiently than sequential DSPs, and the embedded array blocks hold coefficient tables and twiddle-factor ROM. Industrial temperature grading ensures reliability in factory-floor DSP modules. Use the device's PLLs to derive sampling clocks directly from the host reference, eliminating external clock-generation circuitry.
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Industrial Automation Controllers
In factory-automation controllers, the EP20K600CF672I9N integrates motion-control loops, fieldbus interfaces (Profibus, DeviceNet, CAN), and safety-logic functions on a single chip. The industrial temperature range (-40 C to +85 C) and high gate count allow consolidation of what previously required multiple CPLDs. EAB-based memory buffers encoder counters and trajectory tables, while JTAG configuration enables firmware updates during commissioning and field servicing.
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Legacy Protocol Bridges and Bus Converters
The EP20K600CF672I9N is commonly deployed as a bridge between legacy parallel buses (PCI, VME, ISA) and modern serial interfaces in sustaining-engineering programs. Its high I/O count and flexible I/O standard support (LVTTL, LVCMOS, GTL+, PCI) make it ideal for protocol-translation firmware without external glue logic. Designers can preserve the legacy bus while modernizing the serial side, extending the life of installed equipment. The 672-ball FC-FBGA provides sufficient pin density for 64-bit data paths.
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Test and Measurement Instrumentation
The EP20K600CF672I9N's high logic density and embedded memory suit ATE (automatic test equipment) and bench-instrument designs where custom stimulus generation, pattern matching, and timing are required. The LUTs implement fine-grained timing edges while EABs store waveform tables and pattern sequences. Industrial temperature grading allows deployment in production-floor test racks. The JTAG chain enables remote reconfiguration across multiple test stations from a central controller.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K600CF672I9N — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K600CF672I8N | EP20K600CF672I7N | EP20K600CF672C9N | EP20K600CF672C8N | EP20K600CF672C7N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Logic Cells | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| System Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Temperature Grade | Industrial (-40 C to +85 C) | Industrial | Industrial | Commercial | Commercial | Commercial |
| Speed Grade | I9 (fastest I-grade) | I8 | I7 | C9 | C8 | C7 |
주요 차별점
- Highest speed grade in the 600K I-temperature APEX 20KC family (vs EP20K600CF672I8N)
- Industrial temperature range (-40 C to +85 C) for harsh environments (vs EP20K600CF672C9N)
- Same package and footprint as all APEX 20KC 672-FBGA siblings (vs EP20K600CB652C8N)
설계 노트
Power-supply sequencing is critical for the EP20K600CF672I9N: VCCINT (1.8 V core) must rise before or coincident with VCCIO to avoid latch-up. Use a power-good supervisor or sequenced regulator such as the LM3880 to enforce the order, and add 100 µF + 10 µF + 0.1 µF decoupling near each supply pin. Estimated core current at full utilization is approximately 1.5 A, so a 3 A regulator with at least 20 % headroom is recommended.
The 672-ball FC-FBGA package dissipates up to ~3 W under full utilization; a 4-layer PCB with a solid ground plane and thermal via array under the exposed pad is essential. Without thermal vias, junction temperature can exceed 100 C at +85 C ambient, derating performance and accelerating failure. Place at least 25 thermal vias (0.3 mm drill, 1.0 mm pitch) directly under the BGA thermal pad to drop theta-JA from approximately 12 C/W to under 5 C/W.
Route all APEX 20KC I/O banks to the same VCCIO rail to avoid contention; mixing 3.3 V and 2.5 V banks requires separate VCCIO planes. Match impedance for high-speed LVDS or GTL+ traces to 50 ohm single-ended / 100 ohm differential, and keep clock traces under 25 mm with no vias when possible. Series-dampening resistors (33 ohm) at the FPGA clock pins reduce ringing on long traces.
Do not rely on the EP20K600CF672I9N for new designs: this is an NRND part approaching end-of-life. Plan a migration path to a Cyclone IV/V or newer Intel FPGA, or stock sufficient inventory to cover the product lifecycle. When migrating, recompile the Quartus II design with the newer device library, because APEX 20KC primitive libraries are not directly forward-compatible with Cyclone architectures.
규정 준수 정보
Compliance status not explicitly confirmed in the verified web data retrieved on 2026-09-08. The APEX 20KC family was introduced around 2001 and many industrial variants shipped after 2006 are RoHS-compliant, but engineers must verify the specific compliance marking on the device package or request a certificate from the distributor before using the part in RoHS/REACH-mandated designs. AEC-Q100 is not applicable (this is a commercial/industrial FPGA, not an automotive-qualified IC).