EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
부품 번호: EPM7128ATC100-7F ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
EPM7128ATC100-7F 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple SPLDs/GALs and higher-density FPGAs in the programmable logic hierarchy: SPLD < CPLD < FPGA. MAX 7000A devices use second-generation Multiple Array MatriX (MAX) architecture with each LAB containing 16 macrocells, and provide instant-on (zero-power) EEPROM configuration cells, JTAG-based IEEE Std 1149.1 boundary-scan testing, and 3.3V in-system programmability (ISP) through the built-in JTAG interface. Compared with SRAM-based FPGAs, a CPLD boots in microseconds without an external boot PROM, making it ideal for deterministic power-on logic and bus arbitration.
Key features of the EPM7128ATC100-7F include 2.5K usable gates, 128 macrocells, 100 user I/O pins, a 7.5 ns tPD with 116.3 MHz fMAX, 3.0V-3.6V core supply with 2.5V/3.3V multi-voltage I/O support, JTAG IEEE 1149.1 boundary-scan, in-system programmability through JTAG, and four user-defined I/O banks with MultiVolt I/O interfacing. The 100-TQFP (14x14 mm) package is suitable for industrial-temperature (-40C to +85C) designs.
The architecture combines a programmable interconnect array with 16-macrocell LABs, an EEPROM configuration memory, and a JTAG controller; each macrocell contains a programmable AND/OR array, a flip-flop, and product-term allocation logic for combinational or registered logic synthesis. MultiVolt I/O pins tolerate mixed 1.8V/2.5V/3.3V/5V interfaces, allowing direct connection to legacy 5V devices through a simple series resistor or level translator.
Typical applications include PCI/ISA bus interface glue logic, address decoding and chip-select generation, state-machine and sequencer controllers, power-sequencing logic, asynchronous interface bridging (UART, I2C, SPI), legacy 5V-to-3.3V bus translation, and industrial control glue logic. The deterministic 7.5 ns propagation delay is well suited to decode-driven control paths where timing margins must be guaranteed at first silicon.
When designing with this device, plan for a 3.3V core supply (3.0V-3.6V) and a JTAG chain (TCK/TMS/TDI/TDO plus optional TRST) for ISP. Confirm Quartus MAX+PLUS II support for legacy MAX 7000A bitstreams before migrating from older MAX+PLUS toolchains, and reserve four pins for JTAG if boundary-scan is required in production test.
드롭인 대체품: EPM7128ATC100-7F — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM7128ATC100-7F (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, Family, Usable Gates, Process Technology.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM7128ATC100-10
✅ 드롭인✓ 재고 있음
$4.95 / 개
데이터시트 보기 →EPM7128AETI100-7
✅ 드롭인✓ 재고 있음
$30.1 / 개
데이터시트 보기 →EPM7128AETC100-7N
✅ 드롭인✓ 재고 있음
$31.8 / 개
데이터시트 보기 →EPM7128AETC100-10N
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EPM7128AETC100-5N
✅ 드롭인✓ 재고 있음
$6.85 / 개
데이터시트 보기 →EPM7128AETC100-10
✅ 드롭인✓ 재고 있음
$13.85 / 개
데이터시트 보기 →EPM7128ATC100-7F 최대 정격 & 전기적 특성
| Family | MAX 7000A |
| Device | EPM7128A |
| Logic Elements / Macrocells | 128 macrocells |
| Logic Array Blocks (LABs) | 8 |
| Usable Gates | 2.5K |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Internal Frequency (fMAX) | 116.3 MHz |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) |
| Programmable Type | EEPROM (in-system programmable, non-volatile) |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP |
| 패키지 | 100-pin TQFP (14x14 mm) |
| 동작 온도 | -40C to +85C (industrial) |
| Process Technology | CMOS, EEPROM configuration |
| 실장 유형 | Surface Mount |
EPM7128ATC100-7F 핀 구성
| 핀 1 | I/O — User I/O (Bank 1) |
| 핀 2 | I/O — User I/O (Bank 1) |
| 핀 3 | I/O — User I/O (Bank 1) |
| 핀 4 | I/O — User I/O (Bank 1) |
| 핀 5 | I/O — User I/O (Bank 1) |
| 핀 6 | I/O — User I/O (Bank 1) |
| 핀 7 | VCCINT — 3.3V core supply |
| 핀 8 | I/O — User I/O (Bank 1) |
| 핀 9 | I/O — User I/O (Bank 1) |
| 핀 10 | GND — Ground |
| 핀 11 | I/O — User I/O (Bank 1) |
| 핀 12 | I/O — User I/O (Bank 1) |
| 핀 13 | I/O — User I/O (Bank 1) |
| 핀 14 | TDI — JTAG Test Data In |
| 핀 15 | TMS — JTAG Test Mode Select |
| 핀 16 | TCK — JTAG Test Clock |
| 핀 17 | I/O — User I/O (Bank 1) |
| 핀 18 | I/O — User I/O (Bank 1) |
| 핀 19 | I/O — User I/O (Bank 1) |
| 핀 20 | I/O — User I/O (Bank 1) |
| 핀 21 | VCCIO1 — I/O Bank 1 supply (2.5V/3.3V) |
| 핀 22 | GND — Ground |
| 핀 23 | I/O — User I/O (Bank 1) |
| 핀 24 | I/O — User I/O (Bank 1) |
| 핀 25 | I/O — User I/O (Bank 1) |
| 핀 26 | I/O — User I/O (Bank 2) |
| 핀 27 | I/O — User I/O (Bank 2) |
| 핀 28 | I/O — User I/O (Bank 2) |
| 핀 29 | I/O — User I/O (Bank 2) |
| 핀 30 | GND — Ground |
| 핀 31 | I/O — User I/O (Bank 2) |
| 핀 32 | I/O — User I/O (Bank 2) |
| 핀 33 | I/O — User I/O (Bank 2) |
| 핀 34 | I/O — User I/O (Bank 2) |
| 핀 35 | I/O — User I/O (Bank 2) |
| 핀 36 | I/O — User I/O (Bank 2) |
| 핀 37 | VCCIO2 — I/O Bank 2 supply (2.5V/3.3V) |
| 핀 38 | I/O — User I/O (Bank 2) |
| 핀 39 | I/O — User I/O (Bank 2) |
| 핀 40 | I/O — User I/O (Bank 2) |
| 핀 41 | GND — Ground |
| 핀 42 | I/O — User I/O (Bank 2) |
| 핀 43 | I/O — User I/O (Bank 2) |
| 핀 44 | I/O — User I/O (Bank 2) |
| 핀 45 | I/O — User I/O (Bank 2) |
| 핀 46 | I/O — User I/O (Bank 3) |
| 핀 47 | I/O — User I/O (Bank 3) |
| 핀 48 | I/O — User I/O (Bank 3) |
| 핀 49 | I/O — User I/O (Bank 3) |
| 핀 50 | I/O — User I/O (Bank 3) |
| 핀 51 | GND — Ground |
| 핀 52 | I/O — User I/O (Bank 3) |
| 핀 53 | I/O — User I/O (Bank 3) |
| 핀 54 | I/O — User I/O (Bank 3) |
| 핀 55 | I/O — User I/O (Bank 3) |
| 핀 56 | VCCIO3 — I/O Bank 3 supply (2.5V/3.3V) |
| 핀 57 | I/O — User I/O (Bank 3) |
| 핀 58 | I/O — User I/O (Bank 3) |
| 핀 59 | I/O — User I/O (Bank 3) |
| 핀 60 | I/O — User I/O (Bank 3) |
| 핀 61 | I/O — User I/O (Bank 3) |
| 핀 62 | GND — Ground |
| 핀 63 | I/O — User I/O (Bank 3) |
| 핀 64 | I/O — User I/O (Bank 3) |
| 핀 65 | I/O — User I/O (Bank 3) |
| 핀 66 | I/O — User I/O (Bank 3) |
| 핀 67 | I/O — User I/O (Bank 4) |
| 핀 68 | I/O — User I/O (Bank 4) |
| 핀 69 | I/O — User I/O (Bank 4) |
| 핀 70 | I/O — User I/O (Bank 4) |
| 핀 71 | GND — Ground |
| 핀 72 | I/O — User I/O (Bank 4) |
| 핀 73 | I/O — User I/O (Bank 4) |
| 핀 74 | I/O — User I/O (Bank 4) |
| 핀 75 | I/O — User I/O (Bank 4) |
| 핀 76 | VCCIO4 — I/O Bank 4 supply (2.5V/3.3V) |
| 핀 77 | I/O — User I/O (Bank 4) |
| 핀 78 | I/O — User I/O (Bank 4) |
| 핀 79 | I/O — User I/O (Bank 4) |
| 핀 80 | I/O — User I/O (Bank 4) |
| 핀 81 | I/O — User I/O (Bank 4) |
| 핀 82 | I/O — User I/O (Bank 4) |
| 핀 83 | GND — Ground |
| 핀 84 | I/O — User I/O (Bank 4) |
| 핀 85 | I/O — User I/O (Bank 4) |
| 핀 86 | I/O — User I/O (Bank 4) |
| 핀 87 | I/O — User I/O (Bank 4) |
| 핀 88 | I/O — User I/O (Bank 4) |
| 핀 89 | I/O — User I/O (Bank 4) |
| 핀 90 | I/O — User I/O (Bank 4) |
| 핀 91 | GND — Ground |
| 핀 92 | I/O — User I/O (Bank 4) |
| 핀 93 | I/O — User I/O (Bank 4) |
| 핀 94 | TDO — JTAG Test Data Out |
| 핀 95 | I/O — User I/O (Bank 4) |
| 핀 96 | I/O — User I/O (Bank 4) |
| 핀 97 | I/O — User I/O (Bank 1) |
| 핀 98 | I/O — User I/O (Bank 1) |
| 핀 99 | I/O — User I/O (Bank 1) |
| 핀 100 | I/O — User I/O (Bank 1) |
일반적인 애플리케이션
EPM7128ATC100-7F 적합 용도: 6 애플리케이션s: PCI / ISA Bus Glue Logic, Address Decoding & Chip-Select Generation, State Machine & Sequencer Controller, Legacy 5V to 3.3V Bus Translator, Power-Sequencing & Reset Logic, Asynchronous Interface Bridging (UART / SPI / I2C).
PCI / ISA Bus Glue Logic
The EPM7128ATC100-7F is a strong fit for PCI/ISA bus glue logic where deterministic sub-10 ns timing is mandatory: address decoding, chip-select generation, wait-state insertion, and bus arbitration all benefit from the part's 7.5 ns pin-to-pin propagation delay and 116.3 MHz fMAX. With 128 macrocells and 84+ user I/Os, it can replace multiple 74-series glue-logic packages on legacy ISA cards while reducing board area and BOM count. The 3.3V core with 5V-tolerant MultiVolt I/O lets it bridge directly to older 5V peripherals through a simple series resistor, easing migration of legacy industrial PCs without redesigning the entire backplane.
추천
Address Decoding & Chip-Select Generation
Use the EPM7128ATC100-7F as a centralized address decoder to generate chip-select, output-enable, and write-enable signals for memory banks and peripherals sharing a common bus. Each macrocell can implement a wide product-term AND/OR decode, and the device's 100 user I/Os comfortably handle up to a 24-bit address plus 8-bit chip-select fan-out. The 7.5 ns tPD keeps decoded strobes inside a single 33 MHz PCI cycle (30 ns period), eliminating metastability risk and removing the need for an external decoder PAL. Engineers can revision-fix decode bugs in seconds by recompiling the EEPROM bitstream via JTAG.
추천
State Machine & Sequencer Controller
The EPM7128ATC100-7F excels as a finite state machine controller for power-sequencer, motor-control, or industrial-automation logic. Each of its 128 macrocells contains a flip-flop and dedicated product-term allocation logic, allowing up to 128 registered states per device with combinational glue logic on the same die. The non-volatile EEPROM configuration means the sequencer boots in microseconds at power-on - critical for fail-safe controllers where an SRAM-based FPGA would otherwise need an external boot PROM and add tens of milliseconds to startup. Quartus II synthesis of legacy .tdf or .vhd state-machine code yields predictable timing reports that match silicon behavior within one tPD.
추천
Legacy 5V to 3.3V Bus Translator
The EPM7128ATC100-7F's MultiVolt I/O makes it a practical bridge between legacy 5V peripherals and modern 3.3V processors or ASICs. Each I/O bank can be independently powered at 2.5V or 3.3V, and the inputs tolerate 5V signals through a 100 ohm series resistor, eliminating dedicated level-shifter ICs. The CPLD can also implement bidirectional bus switches and direction-control logic in the same device, reducing the bill of materials on mixed-voltage adapter boards. With 84+ I/Os available, a single EPM7128ATC100-7F can translate a full 8/16/32-bit data bus plus handshaking signals in one package.
추천
Power-Sequencing & Reset Logic
Power-sequencing logic for multi-rail systems is a natural fit for the EPM7128ATC100-7F: instant-on EEPROM configuration means rail-ordering signals are valid within microseconds of VCCINT reaching regulation, without the boot delay of an SRAM FPGA. The 7.5 ns tPD supports fast Power-Good cascades and programmable watchdog timers for FPGAs, ASICs, and microprocessors that require specific rail-up/down ordering per their datasheets. Built-in JTAG (IEEE 1149.1) boundary-scan lets production test verify every power-sequencing net is correctly wired before the rest of the board is powered up.
추천
Asynchronous Interface Bridging (UART / SPI / I2C)
Bridging asynchronous peripherals to a host bus is a classic CPLD application, and the EPM7128ATC100-7F brings 128 macrocells and 100 user I/Os to handle multi-channel UART, SPI master/slave, and I2C controller/slave bridges in a single device. Each macrocell implements the bit-banging or state-machine logic with deterministic sub-10 ns timing, which is critical when emulating an I2C master at 400 kHz Fast-mode or driving multiple SPI slaves with precise chip-select skew. Compared with bit-banging on a microcontroller, the CPLD approach offloads deterministic real-time work from the host CPU and runs in parallel without scheduler jitter.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM7128ATC100-7F — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM7128ATC100-10 | EPM7128AETI100-7 | EPM7128AETC100-7N | EPM7128AETC100-5N |
|---|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns | 7.5 ns | 7.5 ns | 5 ns |
| Internal Frequency (fMAX) | 116.3 MHz | 100 MHz (est.) | 116.3 MHz | 116.3 MHz | 147 MHz (est.) |
| Core Voltage | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C (I suffix) | -40C to +85C | -40C to +85C |
| Lead-Free Finish | Yes (F suffix) | Optional (N suffix variants exist) | Optional | Yes (N suffix) | Yes (N suffix) |
주요 차별점
- 7.5 ns grade with industrial-temp 'I' suffix variant available (vs EPM7128ATC100-10)
- Lead-free (F suffix) assembly compliance (vs EPM7128ATC100-7 (leaded))
- Same-package 5 ns grade upgrade path (vs EPM7128AETC100-5N)
설계 노트
The EPM7128ATC100-7F requires a 3.0V-3.6V core supply on VCCINT plus one or more 2.5V/3.3V supplies on the VCCIO bank pins (VCCIO1-VCCIO4). Estimated: at 100% utilization with all 128 macrocells toggling at 116 MHz, the device draws roughly 250-400 mA from VCCINT, so place 0.1 uF X7R decoupling caps within 5 mm of every VCCINT/VCCIO pin and a single 10 uF bulk tantalum near the package. Sharing a 3.3V rail with a noisy switching converter is acceptable for logic but adds jitter to clock nets - keep a ferrite bead between switching and CPLD supplies.
Route JTAG signals (TCK, TMS, TDI, TDO) as a 4-wire daisy-chain with optional TRST, keeping total stub length under 25 mm and using 10 kohm pull-ups on TMS, TDI, and TRST to prevent accidental JTAG state-machine entry at power-up. The 100-pin TQFP has 0.5 mm pitch, which is hand-solderable with a fine tip but requires a hot-plate or reflow profile (ramp 1-2 C/s, peak 245 C, 60 s above 220 C) for reliable assembly. Decoupling caps should sit on the same side as the CPLD to minimize loop inductance.
Common pitfalls with the EPM7128ATC100-7F include: (1) forgetting the JTAG chain reservation when board space is tight - all four JTAG pins must remain accessible for ISP; (2) mixing 5V inputs directly into MultiVolt I/O without a series resistor, which overstresses the input clamp diodes; (3) using the device outside Quartus MAX+PLUS II legacy support, since newer Quartus versions dropped MAX 7000A synthesis - confirm tool support before starting a new design. Also note the part is NRD (Not Recommended for New Designs), so plan a migration path to MAX II or MAX V for new product development.
규정 준수 정보
F suffix indicates lead-free terminal finish per industry convention. RoHS/REACH compliance not explicitly stated in verified web data - check Altera/Intel environmental documentation before qualifying for new designs.