EPM9560RI208-20W - MAX 9000 CPLD, 12K Gates, 208-Pin | Intel
부품 번호: EPM9560RI208-20W ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.2 | $702.00 |
| 100 | $62 | $6,200.00 |
| 500 | $55.5 | $27,750.00 |
| 1,000 | $48.75 | $48,750.00 |
EPM9560RI208-20W 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between discrete glue logic and FPGAs in the design hierarchy. CPLDs use EEPROM or flash configuration memory, providing instant-on behavior at power-up without an external boot ROM. Within the broader programmable logic taxonomy, the EPM9560RI208-20W belongs to: CPLD -> programmable logic -> logic IC -> integrated circuit. The MAX 9000 family uses a hierarchical routing architecture with Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), which optimizes timing predictability for state machine and decoder applications.
Key features include 560 macrocells arranged in 16 Logic Array Blocks (LABs) of 40 macrocells each, 212 user I/O pins, JTAG-based IEEE 1149.1 boundary-scan test support, and 5V in-system programmability. The device supports PCI-compatible I/O and offers multiple speed grades (-10, -12, -15, -20) for trade-off optimization. The 'W' suffix denotes industrial temperature range and specific package/qualification options per Altera ordering codes.
From an architecture perspective, the MAX 9000 uses a coarse-grained macrocell structure where each macrocell contains a programmable AND/OR array with a configurable flip-flop. This differs from FPGA fine-grained look-up-table architectures and gives the MAX 9000 family superior performance for wide combinatorial and registered logic functions at the cost of lower logic density per silicon area.
Typical applications include industrial control glue logic, telecom interface bridging, PCI bus interface controllers, address decoding and bus arbitration, motor control state machines, and legacy 5V system replacements. The wide 5V tolerance makes it compatible with older microprocessors and bus standards.
When designing with this device, ensure your JTAG chain is properly terminated and consider using Altera's legacy MAX+PLUS II or Quartus II tools for synthesis and fitting. The 208-pin RQFP footprint requires substantial PCB area; verify your thermal design at high toggle rates.
This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 9000 family, and practical design notes not collected in the manufacturer datasheet.
드롭인 대체품: EPM9560RI208-20W — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM9560RI208-20W (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, Architecture, In-System Programmability, Configuration Memory.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM9560RI208-20
✅ 드롭인✓ 재고 있음
$21.1 / 개
데이터시트 보기 →EPM9560RI208-20N
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RI208-15
✅ 드롭인✓ 재고 있음
$20.1 / 개
데이터시트 보기 →EPM9560RI208-15N
✅ 드롭인✓ 재고 있음
$19.45 / 개
데이터시트 보기 →EPM9560RI208-10
✅ 드롭인✓ 재고 있음
$67.8 / 개
데이터시트 보기 →EPM9560RI208-10N
✅ 드롭인✓ 재고 있음
$61.75 / 개
데이터시트 보기 →EPM9560RI208-20W 최대 정격 & 전기적 특성
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 LABs of 40 macrocells each |
| User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Counter Frequency (fCNT) | 100 MHz |
| Speed Grade | -20 |
| 공급 전압 | 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | CMOS EEPROM |
| 패키지 | 208-pin RQFP (Power Quad Flat Pack) |
| 동작 온도 | -40C to +85C (Industrial) |
| Architecture | Third-generation Multiple Array MatriX (MAX) |
EPM9560RI208-20W 핀 구성
| 핀 1 | GND — Ground reference |
| 핀 2 | I/O — User I/O pin (LAB bank 1) |
| 핀 3 | I/O — User I/O pin (LAB bank 1) |
| 핀 4 | I/O — User I/O pin (LAB bank 1) |
| 핀 5 | VCC — 5.0V supply voltage |
| 핀 6 | I/O — User I/O pin (LAB bank 1) |
| 핀 7 | I/O — User I/O pin (LAB bank 1) |
| 핀 8 | I/O — User I/O pin (LAB bank 1) |
| 핀 9 | I/O — User I/O pin (LAB bank 1) |
| 핀 10 | I/O — User I/O pin (LAB bank 1) |
| 핀 11 | GND — Ground reference |
| 핀 12 | I/O — User I/O pin (LAB bank 1) |
| 핀 13 | I/O — User I/O pin (LAB bank 1) |
| 핀 14 | I/O — User I/O pin (LAB bank 1) |
| 핀 15 | I/O — User I/O pin (LAB bank 1) |
| 핀 16 | VCC — 5.0V supply voltage |
| 핀 17 | I/O — User I/O pin (LAB bank 1) |
| 핀 18 | I/O — User I/O pin (LAB bank 1) |
| 핀 19 | I/O — User I/O pin (LAB bank 1) |
| 핀 20 | I/O — User I/O pin (LAB bank 1) |
| 핀 21 | GND — Ground reference |
| 핀 22 | I/O — User I/O pin (LAB bank 1) |
| 핀 23 | I/O — User I/O pin (LAB bank 1) |
| 핀 24 | I/O — User I/O pin (LAB bank 1) |
| 핀 25 | I/O — User I/O pin (LAB bank 1) |
| 핀 26 | VCC — 5.0V supply voltage |
| 핀 27 | I/O — User I/O pin (LAB bank 1) |
| 핀 28 | I/O — User I/O pin (LAB bank 1) |
| 핀 29 | I/O — User I/O pin (LAB bank 1) |
| 핀 30 | I/O — User I/O pin (LAB bank 1) |
| 핀 31 | GND — Ground reference |
| 핀 32 | I/O — User I/O pin (LAB bank 2) |
| 핀 33 | I/O — User I/O pin (LAB bank 2) |
| 핀 34 | I/O — User I/O pin (LAB bank 2) |
| 핀 35 | I/O — User I/O pin (LAB bank 2) |
| 핀 36 | VCC — 5.0V supply voltage |
| 핀 37 | I/O — User I/O pin (LAB bank 2) |
| 핀 38 | I/O — User I/O pin (LAB bank 2) |
| 핀 39 | I/O — User I/O pin (LAB bank 2) |
| 핀 40 | I/O — User I/O pin (LAB bank 2) |
| 핀 41 | GND — Ground reference |
| 핀 42 | I/O — User I/O pin (LAB bank 2) |
| 핀 43 | I/O — User I/O pin (LAB bank 2) |
| 핀 44 | I/O — User I/O pin (LAB bank 2) |
| 핀 45 | I/O — User I/O pin (LAB bank 2) |
| 핀 46 | VCC — 5.0V supply voltage |
| 핀 47 | I/O — User I/O pin (LAB bank 2) |
| 핀 48 | I/O — User I/O pin (LAB bank 2) |
| 핀 49 | I/O — User I/O pin (LAB bank 2) |
| 핀 50 | I/O — User I/O pin (LAB bank 2) |
| 핀 51 | GND — Ground reference |
| 핀 52 | I/O — User I/O pin (LAB bank 2) |
| 핀 53 | I/O — User I/O pin (LAB bank 2) |
| 핀 54 | I/O — User I/O pin (LAB bank 2) |
| 핀 55 | I/O — User I/O pin (LAB bank 2) |
| 핀 56 | VCC — 5.0V supply voltage |
| 핀 57 | I/O — User I/O pin (LAB bank 2) |
| 핀 58 | I/O — User I/O pin (LAB bank 2) |
| 핀 59 | I/O — User I/O pin (LAB bank 2) |
| 핀 60 | I/O — User I/O pin (LAB bank 2) |
| 핀 61 | GND — Ground reference |
| 핀 62 | I/O — User I/O pin (LAB bank 3) |
| 핀 63 | I/O — User I/O pin (LAB bank 3) |
| 핀 64 | I/O — User I/O pin (LAB bank 3) |
| 핀 65 | I/O — User I/O pin (LAB bank 3) |
| 핀 66 | VCC — 5.0V supply voltage |
| 핀 67 | I/O — User I/O pin (LAB bank 3) |
| 핀 68 | I/O — User I/O pin (LAB bank 3) |
| 핀 69 | I/O — User I/O pin (LAB bank 3) |
| 핀 70 | I/O — User I/O pin (LAB bank 3) |
| 핀 71 | GND — Ground reference |
| 핀 72 | I/O — User I/O pin (LAB bank 3) |
| 핀 73 | I/O — User I/O pin (LAB bank 3) |
| 핀 74 | I/O — User I/O pin (LAB bank 3) |
| 핀 75 | I/O — User I/O pin (LAB bank 3) |
| 핀 76 | VCC — 5.0V supply voltage |
| 핀 77 | I/O — User I/O pin (LAB bank 3) |
| 핀 78 | I/O — User I/O pin (LAB bank 3) |
| 핀 79 | I/O — User I/O pin (LAB bank 3) |
| 핀 80 | I/O — User I/O pin (LAB bank 3) |
| 핀 81 | GND — Ground reference |
| 핀 82 | I/O — User I/O pin (LAB bank 3) |
| 핀 83 | I/O — User I/O pin (LAB bank 3) |
| 핀 84 | I/O — User I/O pin (LAB bank 3) |
| 핀 85 | I/O — User I/O pin (LAB bank 3) |
| 핀 86 | VCC — 5.0V supply voltage |
| 핀 87 | I/O — User I/O pin (LAB bank 3) |
| 핀 88 | I/O — User I/O pin (LAB bank 3) |
| 핀 89 | I/O — User I/O pin (LAB bank 3) |
| 핀 90 | I/O — User I/O pin (LAB bank 3) |
| 핀 91 | GND — Ground reference |
| 핀 92 | I/O — User I/O pin (LAB bank 4) |
| 핀 93 | I/O — User I/O pin (LAB bank 4) |
| 핀 94 | I/O — User I/O pin (LAB bank 4) |
| 핀 95 | I/O — User I/O pin (LAB bank 4) |
| 핀 96 | VCC — 5.0V supply voltage |
| 핀 97 | I/O — User I/O pin (LAB bank 4) |
| 핀 98 | I/O — User I/O pin (LAB bank 4) |
| 핀 99 | I/O — User I/O pin (LAB bank 4) |
| 핀 100 | I/O — User I/O pin (LAB bank 4) |
| 핀 101 | GND — Ground reference |
| 핀 102 | I/O — User I/O pin (LAB bank 4) |
| 핀 103 | I/O — User I/O pin (LAB bank 4) |
| 핀 104 | I/O — User I/O pin (LAB bank 4) |
| 핀 105 | I/O — User I/O pin (LAB bank 4) |
| 핀 106 | VCC — 5.0V supply voltage |
| 핀 107 | I/O — User I/O pin (LAB bank 4) |
| 핀 108 | I/O — User I/O pin (LAB bank 4) |
| 핀 109 | I/O — User I/O pin (LAB bank 4) |
| 핀 110 | I/O — User I/O pin (LAB bank 4) |
| 핀 111 | GND — Ground reference |
| 핀 112 | I/O — User I/O pin (LAB bank 4) |
| 핀 113 | I/O — User I/O pin (LAB bank 4) |
| 핀 114 | I/O — User I/O pin (LAB bank 4) |
| 핀 115 | I/O — User I/O pin (LAB bank 4) |
| 핀 116 | VCC — 5.0V supply voltage |
| 핀 117 | I/O — User I/O pin (LAB bank 4) |
| 핀 118 | I/O — User I/O pin (LAB bank 4) |
| 핀 119 | I/O — User I/O pin (LAB bank 4) |
| 핀 120 | I/O — User I/O pin (LAB bank 4) |
| 핀 121 | GND — Ground reference |
| 핀 122 | TDI — JTAG Test Data In |
| 핀 123 | TMS — JTAG Test Mode Select |
| 핀 124 | TCK — JTAG Test Clock |
| 핀 125 | TDO — JTAG Test Data Out |
| 핀 126 | I/O — User I/O pin (LAB bank 5) |
| 핀 127 | I/O — User I/O pin (LAB bank 5) |
| 핀 128 | I/O — User I/O pin (LAB bank 5) |
| 핀 129 | VCC — 5.0V supply voltage |
| 핀 130 | I/O — User I/O pin (LAB bank 5) |
| 핀 131 | I/O — User I/O pin (LAB bank 5) |
| 핀 132 | I/O — User I/O pin (LAB bank 5) |
| 핀 133 | I/O — User I/O pin (LAB bank 5) |
| 핀 134 | GND — Ground reference |
| 핀 135 | I/O — User I/O pin (LAB bank 5) |
| 핀 136 | I/O — User I/O pin (LAB bank 5) |
| 핀 137 | I/O — User I/O pin (LAB bank 5) |
| 핀 138 | I/O — User I/O pin (LAB bank 5) |
| 핀 139 | I/O — User I/O pin (LAB bank 5) |
| 핀 140 | VCC — 5.0V supply voltage |
| 핀 141 | I/O — User I/O pin (LAB bank 5) |
| 핀 142 | I/O — User I/O pin (LAB bank 5) |
| 핀 143 | I/O — User I/O pin (LAB bank 5) |
| 핀 144 | I/O — User I/O pin (LAB bank 5) |
| 핀 145 | GND — Ground reference |
| 핀 146 | I/O — User I/O pin (LAB bank 6) |
| 핀 147 | I/O — User I/O pin (LAB bank 6) |
| 핀 148 | I/O — User I/O pin (LAB bank 6) |
| 핀 149 | I/O — User I/O pin (LAB bank 6) |
| 핀 150 | VCC — 5.0V supply voltage |
| 핀 151 | I/O — User I/O pin (LAB bank 6) |
| 핀 152 | I/O — User I/O pin (LAB bank 6) |
| 핀 153 | I/O — User I/O pin (LAB bank 6) |
| 핀 154 | I/O — User I/O pin (LAB bank 6) |
| 핀 155 | GND — Ground reference |
| 핀 156 | I/O — User I/O pin (LAB bank 6) |
| 핀 157 | I/O — User I/O pin (LAB bank 6) |
| 핀 158 | I/O — User I/O pin (LAB bank 6) |
| 핀 159 | I/O — User I/O pin (LAB bank 6) |
| 핀 160 | I/O — User I/O pin (LAB bank 6) |
| 핀 161 | VCC — 5.0V supply voltage |
| 핀 162 | I/O — User I/O pin (LAB bank 6) |
| 핀 163 | I/O — User I/O pin (LAB bank 6) |
| 핀 164 | I/O — User I/O pin (LAB bank 6) |
| 핀 165 | I/O — User I/O pin (LAB bank 6) |
| 핀 166 | GND — Ground reference |
| 핀 167 | I/O — User I/O pin (LAB bank 7) |
| 핀 168 | I/O — User I/O pin (LAB bank 7) |
| 핀 169 | I/O — User I/O pin (LAB bank 7) |
| 핀 170 | I/O — User I/O pin (LAB bank 7) |
| 핀 171 | VCC — 5.0V supply voltage |
| 핀 172 | I/O — User I/O pin (LAB bank 7) |
| 핀 173 | I/O — User I/O pin (LAB bank 7) |
| 핀 174 | I/O — User I/O pin (LAB bank 7) |
| 핀 175 | I/O — User I/O pin (LAB bank 7) |
| 핀 176 | GND — Ground reference |
| 핀 177 | I/O — User I/O pin (LAB bank 7) |
| 핀 178 | I/O — User I/O pin (LAB bank 7) |
| 핀 179 | I/O — User I/O pin (LAB bank 7) |
| 핀 180 | I/O — User I/O pin (LAB bank 7) |
| 핀 181 | I/O — User I/O pin (LAB bank 7) |
| 핀 182 | VCC — 5.0V supply voltage |
| 핀 183 | I/O — User I/O pin (LAB bank 7) |
| 핀 184 | I/O — User I/O pin (LAB bank 7) |
| 핀 185 | I/O — User I/O pin (LAB bank 7) |
| 핀 186 | I/O — User I/O pin (LAB bank 7) |
| 핀 187 | GND — Ground reference |
| 핀 188 | I/O — User I/O pin (LAB bank 8) |
| 핀 189 | I/O — User I/O pin (LAB bank 8) |
| 핀 190 | I/O — User I/O pin (LAB bank 8) |
| 핀 191 | I/O — User I/O pin (LAB bank 8) |
| 핀 192 | VCC — 5.0V supply voltage |
| 핀 193 | I/O — User I/O pin (LAB bank 8) |
| 핀 194 | I/O — User I/O pin (LAB bank 8) |
| 핀 195 | I/O — User I/O pin (LAB bank 8) |
| 핀 196 | I/O — User I/O pin (LAB bank 8) |
| 핀 197 | GND — Ground reference |
| 핀 198 | I/O — User I/O pin (LAB bank 8) |
| 핀 199 | I/O — User I/O pin (LAB bank 8) |
| 핀 200 | I/O — User I/O pin (LAB bank 8) |
| 핀 201 | I/O — User I/O pin (LAB bank 8) |
| 핀 202 | VCC — 5.0V supply voltage |
| 핀 203 | I/O — User I/O pin (LAB bank 8) |
| 핀 204 | I/O — User I/O pin (LAB bank 8) |
| 핀 205 | I/O — User I/O pin (LAB bank 8) |
| 핀 206 | I/O — User I/O pin (LAB bank 8) |
| 핀 207 | GND — Ground reference |
| 핀 208 | OE/nCONFIG — Output Enable / nCONFIG (configuration control) |
일반적인 애플리케이션
EPM9560RI208-20W 적합 용도: 6 애플리케이션s: Industrial Control Glue Logic, PCI Bus Interface Controller, Telecom Interface Bridging, Address Decoding and Bus Arbitration, Motor Control State Machines, Legacy 5V System Replacement.
Industrial Control Glue Logic
The EPM9560RI208-20W is well-suited for industrial control glue logic where 5V tolerance, instant-on EEPROM, and wide operating temperature matter. With 560 macrocells and 212 user I/O pins, it can replace multiple 74HC/74LS discrete logic packages while providing reconfigurable state machines for conveyor sequencing, sensor debouncing, and actuator control. The -40C to +85C industrial range and 5V tolerance align with legacy PLC backplanes and motor-drive control boards.
추천
PCI Bus Interface Controller
The EPM9560RI208-20W's 5V PCI-compatible I/O and 100 MHz counter frequency make it suitable for PCI bus interface controllers in legacy embedded systems. Its 560 macrocells can implement PCI target or master state machines, address decoding, and bus arbitration logic. The JTAG ISP allows in-field firmware updates to adapt to bus protocol revisions. Designers should pair the CPLD with line drivers and follow PCI 2.x timing budgets to remain compliant.
추천
Telecom Interface Bridging
The EPM9560RI208-20W bridges telecom interfaces such as T1/E1, HDB3, and B8ZS encoders/decoders, where deterministic timing and 5V tolerance are required. With 20 ns tPD and 100 MHz fCNT, the device handles serial-to-parallel conversion and framing logic at standard telecom bit rates. The 212 user I/O pins accommodate multiple parallel data buses, and the JTAG interface simplifies board-level test of complex bridge designs across telecom backplanes.
추천
Address Decoding and Bus Arbitration
The EPM9560RI208-20W excels at address decoding and bus arbitration in 5V microprocessor systems, where it can replace dozens of discrete decoder chips with a single reconfigurable device. Its 560 macrocells provide ample capacity for 24-32 bit address decoding, chip-select generation, and wait-state insertion. Instant-on EEPROM ensures the bus is correctly arbitrated at power-up without bootloader delay, critical for boot ROM and memory-mapped peripherals in 80x86, 68k, and PowerPC legacy systems.
추천
Motor Control State Machines
The EPM9560RI208-20W implements deterministic state machines for stepper, BLDC, and servo motor control, where predictable propagation delay is more important than raw gate count. The 20 ns tPD and 100 MHz fCNT support PWM generation at standard motor-drive frequencies up to several hundred kHz. Industrial temperature grade and 5V I/O allow direct interface with 5V gate drivers and Hall-effect sensors, reducing the bill of materials versus discrete 74LS logic.
추천
Legacy 5V System Replacement
The EPM9560RI208-20W serves as a drop-in replacement for obsolete 5V ASICs and legacy PAL/GAL devices in industrial and military systems still operating at 5V logic levels. With EEPROM-based configuration, instant-on behavior, and JTAG ISP, it can modernize fielded equipment without changing the motherboard's 5V power architecture. Its NRND status and 208-pin RQFP footprint match many legacy designs, allowing upgrade paths with minimal board rework.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM9560RI208-20W — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM9560RI208-20 | EPM9560RI208-20N | EPM9560RI208-15 | EPM9560RI208-15N | EPM9560RI208-10 | EPM9560RI208-10N |
|---|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 20 ns | 15 ns | 15 ns | 10 ns | 10 ns |
| Counter Frequency (fCNT) | 100 MHz | 100 MHz | 100 MHz | 118 MHz | 118 MHz | 144 MHz | 144 MHz |
| Speed Grade Suffix | -20 (with W industrial suffix) | -20 | -20N (lead-free) | -15 | -15N (lead-free) | -10 | -10N (lead-free) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
주요 차별점
- W industrial temperature suffix provides -40C to +85C operation (vs EPM9560RC208-20)
- 20 ns tPD provides balanced cost-performance in MAX 9560 family (vs EPM9560RI208-10)
- 208-pin RQFP offers the most widely-supported legacy footprint (vs EPM9560RC240-20)
설계 노트
The 208-pin RQFP package has substantial thermal mass but limited heat dissipation area. At sustained high toggle rates with all 212 user I/O switching simultaneously, junction temperature can rise significantly above ambient. Estimated: with theta_JA of approximately 35 C/W on a standard JEDEC test board, total package dissipation of 1W causes a 35C rise. Ensure PCB thermal vias under the exposed die paddle and adequate copper pour for industrial-grade reliability across -40C to +85C operation.
The 208-pin RQFP footprint requires a 0.5mm lead pitch and 28mm x 28mm PCB land pattern. Place decoupling capacitors (0.1uF ceramic in parallel with 10uF tantalum or polymer) on every VCC pin within 5mm of the package body. Use a ground plane on the layer immediately beneath the device to minimize inductance on the high-current GND pins. Maintain at least 4-layer PCB construction with dedicated power and ground planes for switching-noise-sensitive applications like PCI interfaces.
Do not connect JTAG signals TDI, TMS, TCK, or TDO directly to other digital signals without proper isolation. The MAX 9000 family requires the JTAG chain to be properly terminated with 10k pull-ups on TDI/TMS and that TCK be glitch-free during programming. Failing to observe JTAG chain integrity leads to ISP failures and device lockup. Additionally, do not exceed 5.0V VCC; the device has no internal voltage regulator and direct connection to 3.3V systems requires level shifters on all I/O pins.
규정 준수 정보
RoHS/REACH status not confirmed in verified web data; consult Intel/Altera legacy product documentation. The -20N variants of this family are explicitly lead-free. AEC-Q100 not applicable for this NRND CPLD - choose automotive-qualified alternatives for new automotive designs.