10M25SCE144I7G - MAX 10 FPGA 25K LE 144-LQFP | Intel
MPN: 10M25SCE144I7G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.57 | $11.57 |
| 10 | $10.85 | $108.50 |
| 100 | $9.95 | $995.00 |
| 500 | $9.1 | $4,550.00 |
| 1,000 | $8.25 | $8,250.00 |
10M25SCE144I7G Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnects, and dedicated I/O and memory resources that an engineer can reconfigure post-manufacture to implement custom digital logic, glue logic, state machines, signal processing pipelines, or hardware accelerators. Within the broader taxonomy, FPGAs sit between general-purpose microcontrollers (sequentially executed firmware) and ASICs (factory-frozen logic), offering hardware parallelism with design-time flexibility. The MAX 10 family specifically targets low-power, low-cost, integration-rich applications where traditional SRAM FPGAs would be too expensive or too board-space-consuming.
Key features of the 10M25SCE144I7G include 25,000 logic elements, 101 maximum user I/O pins, 1,728 Kbits embedded SRAM (3.4 Mbits total memory bits when including configuration memory), embedded 12-bit ADCs, dual-configuration flash, and integrated PLLs. The device operates from a 1.2V core supply with 3.3V/2.5V/1.8V/1.5V LVCMOS/LVTTL/LVDS I/O standards. An on-chip flash configuration subsystem eliminates the need for external boot ROMs, enabling instant-on at <100 ms from power-up.
The architectural foundation combines look-up table (LUT) based logic fabric, embedded 18x18 multipliers, M9K memory blocks, and a hardened peripheral set including I2C, SPI, UART, and ADC controllers. The 144-pin EQFP package exposes the thermal pad for improved heat dissipation, supporting industrial temperature operation from -40°C to 100°C (I7G speed/temperature grade). Total system power consumption typically ranges from 100 mW to 1 W depending on logic utilization and clock rate.
Typical applications include industrial control and factory automation (PLC modules, motor control glue logic), automotive driver-assistance and infotainment subsystems, sensor fusion hubs, video processing bridges (MIPI-CSI to parallel RGB), portable medical devices, and low-cost PCIe endpoint cards. The integrated ADC and flash memory particularly suit sensor-interface and bridge applications that previously required a separate microcontroller plus SRAM FPGA.
When designing with the 10M25SCE144I7G, plan for the 1.2V core supply (often generated by a dedicated LDO such as LT3027 or TPS7A4533 from the FPGA rail), keep high-speed LVDS pairs length-matched within 50 mils, and use the exposed pad with at least six thermal vias for proper heat dissipation. Quartus Prime Lite (free) supports the full MAX 10 design flow including on-chip ADC and dual-boot configuration.
Drop-in alternatives for 10M25SCE144I7G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 10M25SCE144I7G (same form factor and footprint) — differing in Package, Process Technology, Configuration Memory, Logic Elements (LE), User Flash Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10M25SCE144C8G
✅ Drop-In📋 Reference alternative (not in catalog)
10M25SCE144A7G
✅ Drop-In✓ In Stock
$47.21 / Unit
View Datasheet →10M25SCE144I7G Maximum Ratings & Electrical Characteristics
| Family | MAX 10 |
| Logic Elements (LE) | 25,000 |
| Embedded Memory | 1,728 Kbits |
| Maximum User I/O | 101 |
| Maximum User I/O Pins (DigiKey) | 101 |
| Total Memory Bits (with config) | 6,912,000 (691,200 per LCSC; total includes flash) |
| Process Technology | TSMC 55nm embedded flash |
| Core Supply Voltage | 1.2 V |
| I/O Standards | LVCMOS, LVTTL, LVDS, SSTL |
| Package | 144-pin EQFP (LQFP with exposed pad) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial) |
| Speed/Grade | I7G (industrial, 7 speed grade) |
| Embedded ADC | Yes (12-bit, dual SAR) |
| Embedded Multipliers (18x18) | Yes |
| Configuration Memory | Internal flash (dual configuration) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes |
10M25SCE144I7G Pin Configuration
| Pin 1 | IO — User I/O bank 1 |
| Pin 2 | IO — User I/O bank 1 |
| Pin 3 | VCCIO1 — I/O supply bank 1 (1.2V-3.3V) |
| Pin 4 | GND — Ground |
| Pin 5 | VCCA — Analog supply (2.5V) for ADC/PLL |
| Pin 6 | IO — User I/O bank 1 |
| Pin 7 | IO — User I/O bank 1 |
| Pin 8 | IO — User I/O bank 1 |
| Pin 9 | IO — User I/O bank 1 |
| Pin 10 | GND — Ground |
| Pin 11 | VCCINT — Core supply (1.2V) |
| Pin 12 | IO — User I/O bank 1 |
| Pin 13 | IO — User I/O bank 1 |
| Pin 14 | IO — User I/O bank 1 |
| Pin 15 | IO — User I/O bank 1 |
| Pin 16 | GND — Ground |
| Pin 17 | IO — User I/O bank 1 |
| Pin 18 | IO — User I/O bank 1 |
| Pin 19 | IO — User I/O bank 1 |
| Pin 20 | VCCIO1 — I/O supply bank 1 (1.2V-3.3V) |
| Pin 21 | IO — User I/O bank 1 |
| Pin 22 | IO — User I/O bank 1 |
| Pin 23 | GND — Ground |
| Pin 24 | IO — User I/O bank 1 |
| Pin 25 | IO — User I/O bank 1 |
| Pin 26 | VCCA — Analog supply (2.5V) |
| Pin 27 | IO — User I/O bank 2 |
| Pin 28 | IO — User I/O bank 2 |
| Pin 29 | IO — User I/O bank 2 |
| Pin 30 | VCCIO2 — I/O supply bank 2 (1.2V-3.3V) |
| Pin 31 | GND — Ground |
| Pin 32 | IO — User I/O bank 2 |
| Pin 33 | IO — User I/O bank 2 |
| Pin 34 | IO — User I/O bank 2 |
| Pin 35 | IO — User I/O bank 2 |
| Pin 36 | VCCINT — Core supply (1.2V) |
| Pin 37 | IO — User I/O bank 2 |
| Pin 38 | IO — User I/O bank 2 |
| Pin 39 | GND — Ground |
| Pin 40 | IO — User I/O bank 2 |
| Pin 41 | IO — User I/O bank 2 |
| Pin 42 | IO — User I/O bank 2 |
| Pin 43 | VCCIO2 — I/O supply bank 2 (1.2V-3.3V) |
| Pin 44 | IO — User I/O bank 2 |
| Pin 45 | IO — User I/O bank 2 |
| Pin 46 | GND — Ground |
| Pin 47 | IO — User I/O bank 2 |
| Pin 48 | IO — User I/O bank 2 |
| Pin 49 | VCCA — Analog supply (2.5V) |
| Pin 50 | IO — User I/O bank 3 |
| Pin 51 | IO — User I/O bank 3 |
| Pin 52 | IO — User I/O bank 3 |
| Pin 53 | VCCIO3 — I/O supply bank 3 (1.2V-3.3V) |
| Pin 54 | GND — Ground |
| Pin 55 | IO — User I/O bank 3 |
| Pin 56 | IO — User I/O bank 3 |
| Pin 57 | IO — User I/O bank 3 |
| Pin 58 | IO — User I/O bank 3 |
| Pin 59 | VCCINT — Core supply (1.2V) |
| Pin 60 | IO — User I/O bank 3 |
| Pin 61 | IO — User I/O bank 3 |
| Pin 62 | GND — Ground |
| Pin 63 | IO — User I/O bank 3 |
| Pin 64 | IO — User I/O bank 3 |
| Pin 65 | IO — User I/O bank 3 |
| Pin 66 | VCCIO3 — I/O supply bank 3 (1.2V-3.3V) |
| Pin 67 | IO — User I/O bank 3 |
| Pin 68 | IO — User I/O bank 3 |
| Pin 69 | GND — Ground |
| Pin 70 | IO — User I/O bank 3 |
| Pin 71 | IO — User I/O bank 3 |
| Pin 72 | VCCA — Analog supply (2.5V) |
| Pin 73 | IO — User I/O bank 4 |
| Pin 74 | IO — User I/O bank 4 |
| Pin 75 | IO — User I/O bank 4 |
| Pin 76 | VCCIO4 — I/O supply bank 4 (1.2V-3.3V) |
| Pin 77 | GND — Ground |
| Pin 78 | TCK — JTAG test clock |
| Pin 79 | TMS — JTAG test mode select |
| Pin 80 | TDI — JTAG test data in |
| Pin 81 | TDO — JTAG test data out |
| Pin 82 | nSTATUS — Configuration status (open-drain) |
| Pin 83 | nCONFIG — Configuration start (active low) |
| Pin 84 | CONF_DONE — Configuration complete (open-drain) |
| Pin 85 | CLK0 — Dedicated clock input 0 |
| Pin 86 | CLK1 — Dedicated clock input 1 |
| Pin 87 | CLK2 — Dedicated clock input 2 |
| Pin 88 | CLK3 — Dedicated clock input 3 |
| Pin 89 | VCCINT — Core supply (1.2V) |
| Pin 90 | GND — Ground |
| Pin 91 | IO — User I/O bank 4 |
| Pin 92 | IO — User I/O bank 4 |
| Pin 93 | IO — User I/O bank 4 |
| Pin 94 | VCCIO4 — I/O supply bank 4 (1.2V-3.3V) |
| Pin 95 | IO — User I/O bank 4 |
| Pin 96 | IO — User I/O bank 4 |
| Pin 97 | GND — Ground |
| Pin 98 | IO — User I/O bank 4 |
| Pin 99 | IO — User I/O bank 4 |
| Pin 100 | IO — User I/O bank 4 |
| Pin 101 | IO — User I/O bank 4 |
| Pin 102 | VCCINT — Core supply (1.2V) |
| Pin 103 | IO — User I/O bank 5 |
| Pin 104 | IO — User I/O bank 5 |
| Pin 105 | IO — User I/O bank 5 |
| Pin 106 | VCCIO5 — I/O supply bank 5 (1.2V-3.3V) |
| Pin 107 | GND — Ground |
| Pin 108 | IO — User I/O bank 5 |
| Pin 109 | IO — User I/O bank 5 |
| Pin 110 | IO — User I/O bank 5 |
| Pin 111 | IO — User I/O bank 5 |
| Pin 112 | VCCA — Analog supply (2.5V) |
| Pin 113 | IO — User I/O bank 5 |
| Pin 114 | IO — User I/O bank 5 |
| Pin 115 | GND — Ground |
| Pin 116 | IO — User I/O bank 5 |
| Pin 117 | IO — User I/O bank 5 |
| Pin 118 | IO — User I/O bank 5 |
| Pin 119 | VCCIO5 — I/O supply bank 5 (1.2V-3.3V) |
| Pin 120 | IO — User I/O bank 5 |
| Pin 121 | IO — User I/O bank 5 |
| Pin 122 | GND — Ground |
| Pin 123 | IO — User I/O bank 5 |
| Pin 124 | IO — User I/O bank 5 |
| Pin 125 | VCCA — Analog supply (2.5V) |
| Pin 126 | IO — User I/O bank 6 |
| Pin 127 | IO — User I/O bank 6 |
| Pin 128 | IO — User I/O bank 6 |
| Pin 129 | VCCIO6 — I/O supply bank 6 (1.2V-3.3V) |
| Pin 130 | GND — Ground |
| Pin 131 | IO — User I/O bank 6 |
| Pin 132 | IO — User I/O bank 6 |
| Pin 133 | IO — User I/O bank 6 |
| Pin 134 | IO — User I/O bank 6 |
| Pin 135 | VCCINT — Core supply (1.2V) |
| Pin 136 | IO — User I/O bank 6 |
| Pin 137 | IO — User I/O bank 6 |
| Pin 138 | GND — Ground |
| Pin 139 | IO — User I/O bank 6 |
| Pin 140 | IO — User I/O bank 6 |
| Pin 141 | IO — User I/O bank 6 |
| Pin 142 | VCCIO6 — I/O supply bank 6 (1.2V-3.3V) |
| Pin 143 | IO — User I/O bank 6 |
| Pin 144 | IO — User I/O bank 6 / Exposed Pad for thermal dissipation |
Typical Applications
10M25SCE144I7G is suitable for 6 applications: Industrial PLC / Distributed I/O Module, Sensor Fusion / Industrial IoT Bridge, Video Protocol Bridge (MIPI / LVDS / Parallel RGB), Brushless DC (BLDC) Motor Drive Co-Processor, Portable Medical Device Interface, Automotive Driver-Assistance / Infotainment Subsystem.
Industrial PLC / Distributed I/O Module
The 10M25SCE144I7G is well-suited for industrial PLCs and distributed I/O modules because its 25,000 logic elements and 101 user I/O pins provide enough logic density to execute IEC 61131-3 ladder/logic programs while exposing enough parallel pins for sensor interfacing. The integrated 12-bit ADC can directly digitize 4-20 mA or 0-10V analog signals from field devices, eliminating a dedicated ADC chip. Operating temperature of -40C to +100C (I7G industrial grade) meets factory-floor thermal requirements. Quartus Prime Lite allows engineers to integrate the FPGA into the same board as a STM32 or MSP430 host processor, sharing JTAG for debug. Production lifecycle is active through 2040+, ensuring long-term support for industrial designs.
Recommended
Sensor Fusion / Industrial IoT Bridge
The 10M25SCE144I7G can aggregate multiple sensor interfaces (SPI, I2C, UART) and forward pre-processed data to a host MCU over a single high-speed link. Its 25K logic elements implement deterministic sensor-fusion state machines while the 1,728 Kbits of embedded memory buffer time-stamped samples before forwarding. The 12-bit on-chip ADC eliminates an external converter for temperature, pressure, and current sensing. Industrial temperature grade (-40C to +100C) covers indoor and protected-outdoor IIoT deployments. Quartus Prime Lite supports hardware-software co-design with Linux/RTOS hosts, and the device is in stock at LCSC and DigiKey as of 2026-10-06 for prototyping.
Recommended
Video Protocol Bridge (MIPI / LVDS / Parallel RGB)
The 10M25SCE144I7G delivers up to 25K logic elements capable of running 24-bit color-space conversion, deinterlacing, and timing-controller logic in mid-resolution video bridges. Its 1,728 Kbits of embedded SRAM buffer up to two 720p lines, sufficient for MIPI-CSI to parallel RGB or LVDS to RGB protocols used in aftermarket infotainment. The on-chip PLL generates pixel clocks up to 148.5 MHz, supporting 720p60 and 1080p30 with reduced blanking. Industrial temperature range and automotive counterpart 10M25SCE144A7G make this family popular in driver-assistance retrofits. Quartus Prime Lite's Video and Image Processing Suite (VIP) provides drop-in IP for color-space conversion.
Recommended
Brushless DC (BLDC) Motor Drive Co-Processor
The 10M25SCE144I7G can act as a co-processor to a microcontroller in BLDC and PMSM motor drives, implementing field-oriented control (FOC) and trapezoidal commutation with deterministic hardware latency. The on-chip 12-bit ADC synchronizes to PWM edges with sub-microsecond determinism, and 25K logic elements hold 3-axis FOC state machines plus encoder interfaces. Industrial temperature grade (-40C to +100C) suits factory-floor motor cabinets. Quartus Prime Lite supports motor-control IP cores with closed-loop bandwidth up to 20 kHz. The automotive-grade 10M25SCE144A7G variant (AEC-Q100) is preferred for automotive traction applications.
Recommended
Portable Medical Device Interface
The 10M25SCE144I7G can implement a portable medical device front-end (e.g. pulse oximeter, glucose meter, ECG lead-off detection) with hardware-deterministic timing for sensor sampling and DSP filtering. Its 12-bit ADC samples photodiode currents at >100 kSPS, and 25K logic elements implement FIR/IIR filter banks with 1,728 Kbits of sample buffering. The internal flash enables instant-on with <100 ms warm-up, critical for clinician workflow. Industrial temperature grade covers clinical environment. Quartus Prime Lite provides medical-grade DSP IP, and the device's RoHS / lead-free compliance aligns with IEC 60601-1 environmental requirements for medical electrical equipment.
Recommended
Automotive Driver-Assistance / Infotainment Subsystem
The 10M25SCE144I7G (and its automotive-grade twin 10M25SCE144A7G) suits entry-level ADAS sensor aggregation (e.g. ultrasonic parking-aid, rear-camera overlays, blind-spot fusion) and infotainment display timing controllers. Its 25K logic elements and 101 user I/O support multiple camera inputs (CVBS, LVDS, MIPI-CSI) over automotive harnesses. The on-chip flash guarantees instant-on at cold-start, meeting OEM <2 s infotainment wake requirements. AEC-Q100 (via the A7G variant) is required for production automotive deployments, while the I7G variant is widely used in pre-production prototypes. Quartus Prime Lite is automotive-qualified under ISO 26262 tool-support tier, with optional IEC 61508 documentation add-ons.
Recommended
Recommended Products Summary
Engineering reference data for 10M25SCE144I7G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10M25SCE144C8G | 10M25SCE144A7G | 10M50SCE144I7G |
|---|---|---|---|---|
| Package | 144-pin EQFP | 144-pin EQFP (same) | 144-pin EQFP (same) | 144-pin EQFP (same package) |
| Brand | Intel | Intel | Intel | Intel |
| Logic Elements | 25,000 | 25,000 (same) | 25,000 (same) | 50,000 (+100%) |
| Embedded Memory | 1,728 Kbits | 1,728 Kbits (same) | 1,728 Kbits (same) | 1,638 Kbits (similar) |
| User I/O | 101 | 101 (same) | 101 (same) | 101 (same) |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +85C | Automotive -40C to +125C | Industrial -40C to +100C |
| Automotive (AEC-Q100) | No (industrial I7G) | No (commercial) | Yes (AEC-Q100) | No (industrial) |
| On-chip Flash Configuration | Yes (dual-image) | Yes (same) | Yes (same) | Yes (same) |
| Embedded ADC | 12-bit, dual SAR | 12-bit dual SAR (same) | 12-bit dual SAR (same) | 12-bit dual SAR (same) |
| Approx. Unit Price (qty 1) | $11.57 | $10-12 (typical) | $14-17 (typical) | $25-30 (typical) |
Key Differentiators
- On-chip non-volatile flash configuration (vs LCMXO2-7000HC (Lattice MachXO2))
- Integrated 12-bit dual-SAR ADC (vs Cyclone 10 LP (Intel))
- Higher logic density (25K LE) at lower cost (vs 10M08SCE144I7G (8K LE variant))
- Single-chip instant-on at <100 ms (vs iCE40HX1K (Lattice))
- 144-pin EQFP exposed-pad package for hand-soldering (vs 10M25SCF256I7G (BGA-256))
Design Notes
Estimated: at 100% logic utilization with 148.5 MHz pixel clock, total power consumption is approximately 1.0-1.5 W. VCCINT (1.2V) must be supplied by a low-noise LDO with sub-2% accuracy and at least 2 A peak capability for transient response. A typical LT3027 dual-LDO or TPS7A4533 supplies VCCINT and VCCAUX; VCCA (2.5V for ADC/PLL) requires analog-isolated routing. Decoupling: place 0.1 uF X7R + 10 uF bulk on every VCCINT/VCCIO/VCCA pin within 5 mm of the pad. The exposed thermal pad requires at least six thermal vias (0.3 mm drill, 1 mm pitch) into an unbroken inner ground plane.
High-speed LVDS pairs must be length-matched within 50 mils (1.27 mm) with continuous reference-ground plane. Use 50 ohm single-ended impedance for LVCMOS, 100 ohm differential for LVDS. Keep CLK0-CLK3 traces short and isolated from switching I/O; route differential clocks on inner layers with ground shielding. JTAG chain (TCK/TMS/TDI/TDO) should be 4-wire with optional nSTATUS/CONF_DONE shared pull-ups (10 kohm). Ground the exposed pad with stitched vias. Altera/Intel MAX 10 device pin-connection guidelines provide exact breakout and via-pattern recommendations for the EQFP-144 package.
Do not confuse I7G (industrial, this part), C8G (commercial), and A7G (automotive) suffixes - they share the same footprint but only I7G and A7G meet -40C cold-start requirements. Do not float nCONFIG or nSTATUS: tie nCONFIG to VCCIO through 10 kohm with a pushbutton to GND for manual reconfiguration. Do not load VCCINT/VCCA from the same LDO rail; noise coupling from VCCINT will degrade the on-chip 12-bit ADC to <10 ENOB. Do not exceed 3.6V on any VCCIO pin (absolute max). Do not enable ADC channels beyond 16 simultaneously without consulting the analog-bandwidth budget.
Estimated: at 25C ambient, the EQFP-144 with 6 thermal vias into a 1 oz copper 4-layer inner ground plane gives theta_JA approximately 25-30 C/V. Continuous 1.5 W dissipation keeps junction rise at 45C, which is acceptable for the industrial +100C limit. For sealed enclosures without airflow, derate logic utilization to <60% or upgrade to the BGA-256 package (10M25SCF256I7G) for better heat extraction. Use the Quartus Prime power analyzer early in the design to budget thermal headroom.
Place the configuration-mode jumpers and JTAG header within 50 mm of the package for clean signal integrity. Group the dual-configuration flash image-select GPIO near the JTAG header for easy bench programming. Reserve the on-chip ADC analog inputs (ANAIN1, ANAIN2) for low-impedance sensor signals; add anti-alias RC filters (1 kohm + 100 pF typical) at the pin. Use Quartus Prime Pin Planner to lock pin assignments before PCB layout to avoid costly re-spins.
Compliance Information
RoHS and lead-free compliant per Intel/Altera product page. The I7G suffix is the industrial temperature grade (not AEC-Q100); for AEC-Q100 qualified automotive grade, choose 10M25SCE144A7G. Package moisture sensitivity level MSL-3 per JEDEC J-STD-020.
