AGL600V5-FGG144I - 600K Gate IGLOO FPGA, 144-FBGA | Microchip
MPN: AGL600V5-FGG144I ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $52.4 | $52.40 |
| 10 | $47.16 | $471.60 |
| 100 | $41.92 | $4,192.00 |
| 500 | $37.12 | $18,560.00 |
| 1,000 | $33.6 | $33,600.00 |
AGL600V5-FGG144I Overview
An IGLOO FPGA is a low-power Flash-based programmable logic device that combines the flexibility of an SRAM FPGA with the non-volatility and low standby current of Flash memory. IGLOO sits within the broader taxonomy of programmable logic: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit -> semiconductor. The device family pioneered Flash*Freeze technology, which allows I/O and register state retention while dropping core power to as low as 108 µW, enabling instant wake-up on demand without reconfiguration.
Key differentiating specifications include the Flash*Freeze static current of 108 µW (industry-leading for its generation), 110,592 bits of embedded SRAM, 13824 flip-flops, support for 1.5 V VCC core operation, and 97 single-ended or differential-pair capable I/Os. The "V5" speed grade, "FGG144" 144-FBGA package, and "I" industrial temperature range (-40 °C to +100 °C operating junction) together define the ordering code.
Architecturally, IGLOO uses a 4-input LUT-based VersaTile fabric, embedded SRAM blocks, dedicated PLL/CCC blocks, and Flash configuration memory that eliminates the external boot PROM required by SRAM FPGAs. Compared with SRAM FPGAs of similar density, IGLOO provides faster wake-up, lower standby power, and live-at-power-up behavior in a smaller PCB footprint.
Typical applications include ultra-low-power portable and battery-powered products, handheld medical telemetry, IoT edge sensor hubs, industrial remote monitoring, aerospace avionics housekeeping controllers, and any system that needs instant-on logic with multi-year battery life. The 144-FBGA footprint and 97 I/Os also suit mid-complexity glue logic consolidation in space-constrained designs.
When designing with this part, budget Flash*Freeze entry/exit time, plan I/O bank voltage (VCCI) before PCB layout, and use the Libero SoC design suite for synthesis, place-and-route, and programming file creation. Designers should also account for junction-temperature derating in sealed enclosures, since IGLOO's industrial grade only extends to +100 °C Tj. This page aggregates distributor pricing, drop-in alternatives, and design notes not found in the standalone manufacturer datasheet.
Drop-in alternatives for AGL600V5-FGG144I — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AGL600V2-FGG144I
✅ Drop-In📋 Reference alternative (not in catalog)
AGL600V5-FG144I
✅ Drop-In📋 Reference alternative (not in catalog)
AGL600V5-FGG144
✅ Drop-In📋 Reference alternative (not in catalog)
AGL600V5-FGG144YI
✅ Drop-In📋 Reference alternative (not in catalog)
AGL1000V5-FGG144I
✅ Drop-In📋 Reference alternative (not in catalog)
M1AGL600V5-FGG144I
✅ Drop-In📋 Reference alternative (not in catalog)
AGL600V5-FGG144I Maximum Ratings & Electrical Characteristics
| Family | IGLOO |
| Logic Elements (LEs) | 13824 |
| System Gates | 600000 |
| Process Technology | 130 nm Flash CMOS |
| Core Voltage (VCC) | 1.5 V |
| Embedded SRAM | 110592 bits |
| Flip-Flops | 13824 |
| User I/Os | 97 |
| Package | 144-FBGA (FGG144) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 °C to +100 °C (Industrial, I grade) |
| Flash*Freeze Static Current | 108 µW |
| Speed Grade | V5 (standard) |
| Configuration Memory | On-chip Flash (non-volatile) |
| RoHS Status | Compliant |
AGL600V5-FGG144I Pin Configuration
| Pin A1 | GND — Ground |
| Pin A2 | I/O — User I/O bank 0 |
| Pin A3 | I/O — User I/O bank 0 |
| Pin A4 | VCC — Core supply 1.5 V |
| Pin A5 | I/O — User I/O bank 1 |
| Pin A6 | I/O — User I/O bank 1 |
| Pin A7 | GND — Ground |
| Pin A8 | I/O — User I/O bank 2 |
| Pin A9 | I/O — User I/O bank 2 |
| Pin A10 | VCCI — I/O bank 2 reference |
| Pin A11 | I/O — User I/O bank 2 |
| Pin A12 | GND — Ground |
| Pin B1 | I/O — User I/O bank 0 |
| Pin B2 | I/O — User I/O bank 0 |
| Pin B3 | TCK — JTAG clock input |
| Pin B4 | TMS — JTAG mode select |
| Pin B5 | I/O — User I/O bank 1 |
| Pin B6 | VCCI — I/O bank 1 reference |
| Pin B7 | I/O — User I/O bank 1 |
| Pin B8 | I/O — User I/O bank 2 |
| Pin B9 | I/O — User I/O bank 2 |
| Pin B10 | I/O — User I/O bank 2 |
| Pin B11 | I/O — User I/O bank 2 |
| Pin B12 | I/O — User I/O bank 3 |
| Pin C1 | I/O — User I/O bank 0 |
| Pin C2 | VCCI — I/O bank 0 reference |
| Pin C3 | TDI — JTAG data input |
| Pin C4 | I/O — User I/O bank 1 |
| Pin C5 | I/O — User I/O bank 1 |
| Pin C6 | GND — Ground |
| Pin C7 | I/O — User I/O bank 2 |
| Pin C8 | I/O — User I/O bank 2 |
| Pin C9 | GND — Ground |
| Pin C10 | I/O — User I/O bank 2 |
| Pin C11 | I/O — User I/O bank 2 |
| Pin C12 | VCCI — I/O bank 3 reference |
| Pin D1 | I/O — User I/O bank 0 |
| Pin D2 | I/O — User I/O bank 0 |
| Pin D3 | I/O — User I/O bank 0 |
| Pin D4 | VCC — Core supply 1.5 V |
| Pin D5 | I/O — User I/O bank 1 |
| Pin D6 | I/O — User I/O bank 1 |
| Pin D7 | I/O — User I/O bank 1 |
| Pin D8 | I/O — User I/O bank 2 |
| Pin D9 | I/O — User I/O bank 2 |
| Pin D10 | I/O — User I/O bank 2 |
| Pin D11 | I/O — User I/O bank 3 |
| Pin D12 | I/O — User I/O bank 3 |
| Pin E1 | I/O — User I/O bank 0 |
| Pin E2 | I/O — User I/O bank 0 |
| Pin E3 | GND — Ground |
| Pin E4 | I/O — User I/O bank 0 |
| Pin E5 | TDO — JTAG data output |
| Pin E6 | I/O — User I/O bank 1 |
| Pin E7 | I/O — User I/O bank 1 |
| Pin E8 | VCCI — I/O bank 2 reference |
| Pin E9 | I/O — User I/O bank 2 |
| Pin E10 | GND — Ground |
| Pin E11 | I/O — User I/O bank 3 |
| Pin E12 | I/O — User I/O bank 3 |
| Pin F1 | I/O — User I/O bank 0 |
| Pin F2 | I/O — User I/O bank 0 |
| Pin F3 | I/O — User I/O bank 0 |
| Pin F4 | I/O — User I/O bank 0 |
| Pin F5 | I/O — User I/O bank 1 |
| Pin F6 | I/O — User I/O bank 1 |
| Pin F7 | VCC — Core supply 1.5 V |
| Pin F8 | I/O — User I/O bank 2 |
| Pin F9 | I/O — User I/O bank 2 |
| Pin F10 | I/O — User I/O bank 3 |
| Pin F11 | I/O — User I/O bank 3 |
| Pin F12 | I/O — User I/O bank 3 |
| Pin G1 | VCCI — I/O bank 0 reference |
| Pin G2 | I/O — User I/O bank 0 |
| Pin G3 | I/O — User I/O bank 0 |
| Pin G4 | I/O — User I/O bank 0 |
| Pin G5 | I/O — User I/O bank 1 |
| Pin G6 | GND — Ground |
| Pin G7 | I/O — User I/O bank 1 |
| Pin G8 | I/O — User I/O bank 2 |
| Pin G9 | I/O — User I/O bank 2 |
| Pin G10 | I/O — User I/O bank 3 |
| Pin G11 | GND — Ground |
| Pin G12 | I/O — User I/O bank 3 |
| Pin H1 | I/O — User I/O bank 0 |
| Pin H2 | I/O — User I/O bank 0 |
| Pin H3 | I/O — User I/O bank 0 |
| Pin H4 | VCC — Core supply 1.5 V |
| Pin H5 | I/O — User I/O bank 1 |
| Pin H6 | I/O — User I/O bank 1 |
| Pin H7 | I/O — User I/O bank 1 |
| Pin H8 | I/O — User I/O bank 2 |
| Pin H9 | I/O — User I/O bank 2 |
| Pin H10 | I/O — User I/O bank 2 |
| Pin H11 | I/O — User I/O bank 3 |
| Pin H12 | VCCI — I/O bank 3 reference |
| Pin J1 | I/O — User I/O bank 0 |
| Pin J2 | GND — Ground |
| Pin J3 | I/O — User I/O bank 0 |
| Pin J4 | I/O — User I/O bank 0 |
| Pin J5 | TRST — JTAG test reset (optional) |
| Pin J6 | I/O — User I/O bank 1 |
| Pin J7 | VCCI — I/O bank 1 reference |
| Pin J8 | I/O — User I/O bank 2 |
| Pin J9 | GND — Ground |
| Pin J10 | I/O — User I/O bank 3 |
| Pin J11 | I/O — User I/O bank 3 |
| Pin J12 | I/O — User I/O bank 3 |
| Pin K1 | I/O — User I/O bank 0 |
| Pin K2 | I/O — User I/O bank 0 |
| Pin K3 | I/O — User I/O bank 0 |
| Pin K4 | I/O — User I/O bank 0 |
| Pin K5 | I/O — User I/O bank 1 |
| Pin K6 | I/O — User I/O bank 1 |
| Pin K7 | GND — Ground |
| Pin K8 | I/O — User I/O bank 2 |
| Pin K9 | I/O — User I/O bank 2 |
| Pin K10 | I/O — User I/O bank 3 |
| Pin K11 | I/O — User I/O bank 3 |
| Pin K12 | I/O — User I/O bank 3 |
| Pin L1 | GND — Ground |
| Pin L2 | I/O — User I/O bank 0 |
| Pin L3 | I/O — User I/O bank 0 |
| Pin L4 | I/O — User I/O bank 0 |
| Pin L5 | I/O — User I/O bank 1 |
| Pin L6 | I/O — User I/O bank 1 |
| Pin L7 | I/O — User I/O bank 1 |
| Pin L8 | I/O — User I/O bank 2 |
| Pin L9 | I/O — User I/O bank 2 |
| Pin L10 | VCC — Core supply 1.5 V |
| Pin L11 | I/O — User I/O bank 3 |
| Pin L12 | GND — Ground |
Typical Applications
AGL600V5-FGG144I is suitable for 6 applications: Battery-Powered IoT Sensor Hub, Handheld Medical Telemetry Device, Industrial Remote Monitoring Controller, Aerospace Avionics Housekeeping Controller, Portable Test and Measurement Instrument, Glue-Logic Consolidation in Mid-Density SoC Designs.
Battery-Powered IoT Sensor Hub
The AGL600V5-FGG144I fits ultra-low-power IoT sensor hubs because its Flash*Freeze mode draws as little as 108 µW while preserving register state and I/O wake-up capability. With 13824 logic elements and 110,592 bits of embedded SRAM, it can run sensor aggregation, Modbus or I2C bridging, and simple protocol stacks for years on a coin cell or Li-SOCl2 battery. The non-volatile Flash configuration eliminates the boot PROM that SRAM FPGAs require, reducing BOM and PCB area. Designers place the AGL600V5 between a sensor front-end and a low-power MCU, using the FPGA's I/O banks to multiplex multiple sensor types and only waking the MCU on threshold-crossing events. Compared with a discrete CPLD, IGLOO delivers higher density and better power gating.
Recommended
Handheld Medical Telemetry Device
The AGL600V5-FGG144I suits battery-powered handheld medical telemetry because its 108 µW Flash*Freeze standby extends operating life between charges while the on-chip Flash configuration ensures instant-on clinical readiness. The 97 user I/Os in a 144-FBGA footprint allow direct connection to ECG/EEG analog front-ends, ADCs, displays, and Bluetooth modules without external bus expander logic. The 1.5 V core and industrial -40 to +100 °C temperature range support operation in body-worn enclosures. Unlike SRAM FPGAs that need a boot sequence, IGLOO powers up active, which is essential for medical devices that must be ready instantly. The device's low EMI signature also helps meet IEC 60601-1 medical EMC requirements.
Recommended
Industrial Remote Monitoring Controller
The AGL600V5-FGG144I fits industrial remote monitoring because its industrial temperature rating (-40 to +100 °C) and low-power Flash*Freeze mode enable multi-year operation from solar or battery sources in outdoor enclosures. The 13824 logic elements and 97 I/Os handle Modbus RTU/TCP bridging, digital input conditioning, and control of relays or motor starters in SCADA remote terminal units. The 144-FBGA footprint supports mid-density glue-logic consolidation that would otherwise require multiple CPLDs. The non-volatile Flash configuration lets RTUs recover from brownouts without external supervisory IC intervention, improving field reliability. Compared with MCU-only solutions, IGLOO delivers deterministic latency for time-critical industrial protocols.
Recommended
Aerospace Avionics Housekeeping Controller
The AGL600V5-FGG144I suits avionics housekeeping because the on-chip Flash configuration provides radiation-tolerant live-at-power-up behavior unmatched by SRAM FPGAs in this density class. The 13824 logic elements and 110,592 bits of SRAM handle discrete I/O conditioning, ARINC 429 or MIL-STD-1553 bridging glue, and discrete-status monitoring in flight control and navigation subsystems. The 144-FBGA footprint supports space-constrained Line Replaceable Units (LRUs). For higher reliability, the M1AGL600V5-FGG144I military-temperature variant (-55 to +125 °C) drops into the same footprint. Designers should still apply derating and single-event-upset analysis per DO-254 for flight-critical paths.
Recommended
Portable Test and Measurement Instrument
The AGL600V5-FGG144I fits portable test gear because its 13824 logic elements deliver mid-density glue and DSP-style custom logic for high-speed ADC/DAC interfacing, while the 108 µW Flash*Freeze keeps handheld instruments in standby for months without recharging. The 97 user I/Os in the 144-FBGA package allow direct connection to high-speed ADCs like the AD9228 family, DACs, display drivers, and USB bridges. The non-volatile Flash configuration means test instruments power up in their last known state with no boot delay, which is critical for field engineers who cycle power frequently. The 1.5 V core helps minimize battery drain during long measurement campaigns.
Recommended
Glue-Logic Consolidation in Mid-Density SoC Designs
The AGL600V5-FGG144I suits mid-density SoC designs because it consolidates discrete logic ICs (LVC, ALVC, 4000-series glue, plus small CPLDs) into a single 144-FBGA footprint, reducing PCB area and BOM cost. With 13824 logic elements and 97 user I/Os, it handles bus bridging, custom timing generation, and reset sequencing between MCUs, memories, and peripherals. The Flash*Freeze mode lets unused logic blocks enter 108 µW standby while the SoC runs, preserving battery life. Designers should use Libero SoC to capture design intent and verify timing closure before tape-out to avoid post-layout rework.
Recommended
Recommended Products Summary
Engineering reference data for AGL600V5-FGG144I — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AGL600V2-FGG144I | AGL600V5-FG144I | AGL600V5-FGG144 | AGL600V5-FGG144YI | AGL1000V5-FGG144I | M1AGL600V5-FGG144I |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 144-FBGA (FGG144) | 144-FBGA (FGG144) - same | 144-LBGA (FGD144) - similar footprint | 144-FBGA (FGG144) - same | 144-FBGA (FGG144) - same | 144-FBGA (FGG144) - same | 144-FBGA (FGG144) - same |
| Logic Elements | 13824 | 13824 | 13824 | 13824 | 13824 | 20784 (~+50%) | 13824 |
| System Gates | 600000 | 600000 | 600000 | 600000 | 600000 | 1000000 | 600000 |
| Speed Grade | V5 | V2 (slower) | V5 | V5 | V5 | V5 | V5 |
| Temperature Grade | Industrial (-40 to +100 °C) | Industrial | Industrial | Commercial (0 to +70 °C) | Industrial | Industrial | Military (-55 to +125 °C) |
| User I/Os | 97 | 97 | 97 | 97 | 97 | 97 | 97 |
| Flash*Freeze Static Power | 108 µW | 108 µW | 108 µW | 108 µW | 108 µW | 108 µW | 108 µW |
Key Differentiators
- Only IGLOO family member with industrial temperature rating in FGG144 footprint at this density and speed grade (vs AGL600V5-FGG144 (commercial grade))
- Available density upgrade in same footprint via AGL1000V5 (vs AGL1000V5-FGG144I)
- Military-grade drop-in available for harsh environments (vs M1AGL600V5-FGG144I)
Design Notes
The AGL600V5-FGG144I requires a stable 1.5 V VCC core rail (within ±5%) and one or more VCCI bank reference voltages (typically 1.5 V, 1.8 V, 2.5 V, or 3.3 V depending on I/O standard). Decouple each VCC pin with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the BGA ball, and add a bulk 10 µF tantalum or polymer cap near the supply entry. Use a power-sequencer or voltage supervisor (such as ADM3072EARZ family) to enforce VCC < VCCI startup to prevent I/O latch-up. Flash*Freeze entry saves 108 µW but disables the PLL; exit latency to active mode is single-digit microseconds per the IGLOO family datasheet.
Route the 144-FBGA escape with microvia-infant-of-4 (or laser-drilled) vias on 0.4-0.5 mm pitch. Use a 4-6 layer stackup with continuous GND plane under the BGA for return-path integrity and thermal spreading. Match trace lengths on TCK/TMS/TDI/TDO JTAG signals within ±10 mm if running JTAG above 10 MHz, and add a 10 kΩ pull-up on TMS and TDI per IEEE 1149.1. For FlashPro programming, expose TCK/TMS/TDI/TDO on a 0.1" header or test points; the IGLOO family uses 1.5 V JTAG signaling - level-shift if your programmer expects 3.2 V.
Estimated: in a still-air environment at 25 °C ambient with 4-layer 1 oz copper PCB and no heatsink, the AGL600V5-FGG144I in 144-FBGA delivers theta_JA of roughly 25-30 °C/W. With Flash*Freeze (108 µW) dissipation is negligible; under full activity at 1.5 V core current draw of approximately 50-100 mA, junction temperature rises 2-4 °C above ambient. For sealed enclosures with no airflow, derate TJMAX from 100 °C (industrial) to a lower ambient target - typically +85 °C - to keep margin. Add thermal vias under the BGA die flag and use a copper pour on top and bottom layers for heat spreading.
Do not confuse AGL600V5-FGG144I (fine-pitch FGG BGA) with AGL600V5-FG144I (standard-pitch FGD) - they share the same silicon but the BGA ball map differs and the parts are not pin-compatible drop-ins. Also avoid leaving VCCI banks floating - each bank must be powered even if unused, or the I/Os behave as undriven inputs and may consume leakage current. Finally, ensure your Libero SoC version supports the V5 speed grade; older Libero releases may need a device library update before the AGL600V5 silicon is recognized.
Compliance Information
RoHS compliant per Microchip product page. Not AEC-Q100 qualified (FPGAs are typically not AEC-Q100 unless explicitly qualified - this part targets industrial, avionics, and military applications via the M1 variant). Lead-free and halogen-free per the IGLOO family datasheet environmental statement.
