EP1S60B956C6 - Stratix 57K LE FPGA, 683 I/O, 956-BGA | Altera
MPN: EP1S60B956C6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $511.44 | $511.44 |
| 10 | $487.21 | $4,872.10 |
| 100 | $425.89 | $42,589.00 |
| 500 | $378.5 | $189,250.00 |
| 1,000 | $339.2 | $339,200.00 |
Drop-in alternatives for EP1S60B956C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1S40B956C6
✅ Drop-In✓ In Stock
$1078.4 / Unit
View Datasheet →EP1S40B956C6N
✅ Drop-In✓ In Stock
$1050 / Unit
View Datasheet →EP1S30B956C6
✅ Drop-In✓ In Stock
$78 / Unit
View Datasheet →EP1S60B956C6 Maximum Ratings & Electrical Characteristics
| Series | Stratix (EP1S) |
| Logic Elements | 57,120 |
| Total RAM Bits | 5,215,104 |
| Number of LABs/CLBs | 5712 |
| Number of I/O | 683 |
| Package | 956-BBGA, FCBGA (40 x 40 mm) |
| Supplier Device Package | 956-BGA (40x40) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0 C to +85 C (Commercial) |
| Core Voltage - Supply | 1.425 V to 1.575 V |
| Voltage - Supply | 1.425 V to 1.575 V |
| Number of Pins | 956 |
| Form of Terminal | Ball (BGA) |
| Package Code | BGA / FCBGA |
EP1S60B956C6 Pin Configuration
| Pin 1 | I/O Bank 1 — User I/O (refer to datasheet pin table for specific ball) |
| Pin 100 | VCCIO1 — I/O bank 1 supply reference |
| Pin 200 | I/O Bank 2 — User I/O |
| Pin 300 | VCCINT — Core supply 1.425V-1.575V |
| Pin 400 | I/O Bank 3 — User I/O |
| Pin 500 | GND — Ground reference |
| Pin 600 | I/O Bank 4 — User I/O |
| Pin 700 | CLK0 — Dedicated clock input 0 |
| Pin 800 | I/O Bank 5 — User I/O |
| Pin 900 | TCK — JTAG test clock (dedicated) |
| Pin 950 | VCCIO — I/O bank supply |
| Pin 956 | GND — Ground reference |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S60B956C6 is suitable for 6 applications: ASIC Prototyping, Telecommunications Line Cards, High-Speed DSP Pipelines, Software-Defined Radio Baseband, Video and Image Processing, Test & Measurement Instrumentation.
ASIC Prototyping
The EP1S60B956C6 is well-suited to ASIC prototyping because it offers 57,120 logic elements and 5,215,104 bits of embedded RAM in a single 956-BGA package. Engineers can map multi-million-gate ASIC designs directly onto the EP1S60's logic fabric with timing-accurate paths, then validate in-system before tape-out. The 683 user I/Os allow direct breakout of even the largest ASIC pin counts, while the 12 PLLs and multi-voltage I/O banks support mixed ASIC peripheral interfaces without external level translation.
Recommended
Telecommunications Line Cards
In telecom line-card applications, the EP1S60B956C6's combination of high logic density, 683 I/Os, and dedicated DSP blocks makes it ideal for framer/mapper/forward-error-correction pipelines. The 1.5 V core plus multi-standard support (LVDS, HSTL, SSTL, LVTTL) allows direct connection to network processors, SERDES chips, and backplane transceivers. Embedded TriMatrix memory provides per-channel buffering at line rate, while the 12 PLLs generate the multiple clock domains required for OC-48/STM-16 and OTU-1 interfaces.
Recommended
High-Speed DSP Pipelines
For DSP applications such as FIR filters, FFT engines, and baseband processing, the EP1S60B956C6's hard DSP blocks deliver 9/18/36-bit multiply-accumulate at high clock rates. With 5,215,104 bits of TriMatrix memory, designers can hold coefficient tables and sample buffers on-chip to avoid external memory bottlenecks. The 956-BGA package supports the high pin density required for parallel multi-channel data paths, while 12 PLLs provide the clock trees needed for synchronous multi-rate DSP chains.
Recommended
Software-Defined Radio Baseband
The EP1S60B956C6 is a strong match for software-defined radio baseband processing where the device must run FFTs, channelizers, and modulator chains in real time. Its 57,120 logic elements support multi-channel digital down/up-conversion, and the embedded DSP blocks accelerate the multiply-accumulate operations common in polyphase filter banks. The 683 I/Os accommodate parallel ADC/DAC interfaces (LVDS) plus control paths, and the high TriMatrix memory depth supports large sample buffers between the radio front end and baseband DSP chain.
Recommended
Video and Image Processing
For video broadcast and image processing pipelines, the EP1S60B956C6 supports real-time HD video processing thanks to its 683 I/Os for parallel pixel buses and 5.2 Mbit of embedded memory for line buffers. The DSP blocks enable motion estimation, deinterlacing, and scaling kernels to run in hardware without off-chip DSP assistance. The 956-BGA package's 1.0 mm ball pitch is well-suited to multi-layer video boards with controlled-impedance trace routing, and the multiple PLLs generate pixel clocks and memory clocks independently.
Recommended
Test & Measurement Instrumentation
In test & measurement instruments such as logic analyzers, protocol analyzers, and arbitrary waveform generators, the EP1S60B956C6 delivers the I/O count and logic density required for high-channel-count capture and pattern generation. Its 683 I/Os handle multi-channel LVDS data acquisition at hundreds of megabits per second, while the embedded TriMatrix memory acts as deep capture buffer. The 12 PLLs and multi-voltage I/O banks simplify interfacing to mixed-logic-family DUTs, reducing external level-shift components.
Recommended
Recommended Products Summary
Engineering reference data for EP1S60B956C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S40B956C6 | EP1S40B956C6N | EP1S30B956C6 | EP1S25F1020C6 |
|---|---|---|---|---|---|
| Package | 956-BBGA, FCBGA (40x40 mm) | 956-BBGA, FCBGA (40x40 mm) - same | 956-BBGA, FCBGA (40x40 mm) - same | 956-BBGA, FCBGA (40x40 mm) - same | 1020-FBGA - different |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 57,120 | ~41,250 (-28%) | ~41,250 (-28%) | ~33,330 (-42%) | ~25,660 (-55%) |
| Total RAM Bits | 5,215,104 | 3,423,744 | 3,423,744 | 2,215,104 | 1,944,576 |
| Number of I/O | 683 | 683 (same) | 683 (same) | 683 (same) | 683 (same family) |
| Core Voltage | 1.425 V to 1.575 V | 1.425 V to 1.575 V | 1.425 V to 1.575 V | 1.425 V to 1.575 V | 1.425 V to 1.575 V |
| Operating Temperature | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C |
| Unit Price (1 pc, as of 2026-09-07) | USD 511.44 | [DATA_NEEDED: current quote] | [DATA_NEEDED: current quote] | [DATA_NEEDED: current quote] | [DATA_NEEDED: current quote] |
Key Differentiators
- Highest logic density in Stratix-I 956-BGA family (vs EP1S40B956C6)
- Maximum embedded memory in 956-BGA Stratix family (vs EP1S30B956C6)
- Same footprint across the 956-BGA Stratix density ladder (vs EP1S25F1020C6)
Design Notes
Estimated: at VCCINT = 1.5 V and ICC typical of approximately 1.5 A for EP1S60, the core power dissipation can exceed 2 W. Combined with I/O bank power dissipation, total package dissipation can reach 5-8 W. The 956-FCBGA package requires PCB thermal vias under the central ball array and a copper spreader or heatsink to keep junction temperature below 85 C. Always measure with a thermal probe on the package top during worst-case utilization.
The 956-FCBGA has 1.0 mm ball pitch and requires microvia (laser-drilled) PCB technology. Use 4 to 6 PCB layers minimum with dedicated power and ground planes adjacent to the BGA. Decoupling: place 0.1 uF and 0.01 uF X7R ceramic capacitors on every VCCINT and VCCIO pin within 5 mm of the ball, plus bulk 22 uF to 100 uF tantalum or polymer capacitors at each plane edge. Matched-impedance routing is mandatory for LVDS pairs.
Stratix-I configuration requires a configuration device (EPCS1/EPCS4) or JTAG download cable. Common pitfalls: (1) leaving MSEL pins at default selects the wrong configuration mode; (2) ignoring the nCONFIG/nSTATUS handshake during multi-device configuration chains; (3) failing to provide a clean 100 MHz reference clock to the dedicated CLK pins before the I/O banks are configured; (5) using non-1.5 V tolerant I/O standards on banks without proper VCCIO rail. Always sequence power rails in the order specified in the datasheet.
Stratix-I I/O banks are grouped by voltage reference (VCCIO). Group LVDS pairs in the same bank to avoid skew between banks. Use the Quartus II Pin Planner to assign pins before PCB layout begins, then lock the pinout. Differential pair matching should target 10 mil mismatch or less for LVDS at 500+ Mbps. Place external memory (DDR SDRAM) on the same PCB side as the FPGA with matched trace lengths to the FPGA memory interface pins.
Compliance Information
EP1S60B956C6 was launched before RoHS was widely enforced on FPGAs. Distributor listings do not explicitly state RoHS or REACH compliance as of 2026-09-07; treat all compliance fields as [DATA_NEEDED] until an Altera/Intel RoHS/REACH certificate is located. AEC-Q100 is not applicable because this is a commercial-grade FPGA, not an automotive-qualified part.
