EP1S60F1020C6NAA - Stratix FPGA, 57K LEs, 1020-BGA | Intel
MPN: EP1S60F1020C6NAA ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $195 | $19,500.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $145 | $145,000.00 |
Drop-in alternatives for EP1S60F1020C6NAA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1S60F1020C6NAA Maximum Ratings & Electrical Characteristics
| Family | Stratix |
| Series | EP1S60 |
| Logic Elements | 57,120 |
| Total RAM Bits | 5,215,104 |
| Embedded Multipliers | 192 (18x18) |
| Maximum User I/O Pins | 773 |
| Number of LABs/CLBs | 4,510 |
| Number of Logic Cells | 57,120 |
| Operating Temperature | 0C to +85C (commercial) |
| Package | 1020-BBGA (FineLine BGA), 33x33 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount |
| Process Node | 0.13 µm CMOS |
| Voltage - Core | 1.5 V |
| Voltage - I/O | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| Speed Grade | C6 |
| Lead-Free / RoHS | Yes (N suffix) |
| Configuration Scheme | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | 12 |
| Global Clocks | 40 |
EP1S60F1020C6NAA Pin Configuration
| Pin AB24 | I/O Bank 7 — User I/O, bank 7 |
| Pin AC26 | I/O Bank 8 — User I/O, bank 8 |
| Pin G32 | GND — Ground reference |
| Pin H30 | VCCINT — Core supply 1.5V |
| Pin K29 | VCCAUX — Auxiliary supply 1.5V/1.8V |
| Pin M28 | VCCIO1 — I/O bank 1 supply |
| Pin P32 | TCK — JTAG clock |
| Pin R30 | TDI — JTAG data in |
| Pin T28 | TDO — JTAG data out |
| Pin U26 | TMS — JTAG mode select |
| Pin W32 | MSEL0 — Configuration mode select 0 |
| Pin Y30 | MSEL1 — Configuration mode select 1 |
| Pin AA28 | MSEL2 — Configuration mode select 2 |
| Pin AC32 | nSTATUS — Configuration status (active-low) |
| Pin AE30 | CONF_DONE — Configuration done |
| Pin AG32 | DCLK — Configuration clock |
| Pin AJ30 | DATA0 — Configuration data |
| Pin AK28 | nCONFIG — Configuration start (active-low) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S60F1020C6NAA is suitable for 6 applications: Telecom Linecard Interface Logic, High-Speed Serial Protocol Bridging, ASIC Prototyping and Emulation, Digital Video Broadcast / Image Processing, Test and Measurement Instrumentation, Industrial High-Speed Control.
Telecom Linecard Interface Logic
The EP1S60F1020C6NAA's 57,120 logic elements, 5.2 Mbit TriMatrix memory, and 773 user I/O pins fit telecom linecard designs requiring multi-protocol bridging and packet buffering. The C6 speed grade comfortably meets SPI-4.2 / POS-PHY Level 4 timing at typical line rates, while the dedicated 18x18 multipliers support forward-error-correction DSP blocks. The 1020-BGA delivers the I/O density required for 10+ interface ports per board. Compared to a Stratix V migration target, the EP1S60F1020C6NAA offers ample headroom for legacy linecard retrofits without PCB rework.
Recommended
High-Speed Serial Protocol Bridging
Stratix EP1S60F1020C6NAA supports up to 6.5 Gbps embedded transceivers (in C5/C6 speed grades) for SPI-4.2, POS-PHY, Serial RapidIO, and custom serial backplanes. The 12 PLLs provide eight output taps each, enabling multi-clock domain serial-link aggregation. The 192 18x18 hardware multipliers accelerate 8B/10B encoding, scrambling, and CRC blocks. Used as a backplane bridge, the EP1S60F1020C6NAA replaces multiple ASSP PHY chips with a single reprogrammable fabric, lowering BOM cost while preserving upgrade flexibility.
Recommended
ASIC Prototyping and Emulation
With 57,120 logic elements and 5.2 Mbit embedded memory, the EP1S60F1020C6NAA can emulate mid-size ASIC RTL at near-ASIC clock rates. Multiple EP1S60F1020C6NAA devices can be partitioned into one large virtual ASIC via the Stratix 'multi-FPGA' prototyping flow in Quartus II. The TriMatrix blocks model SRAM/ROM while the 18x18 multipliers emulate DSP functions. For production ASIC prototypes requiring hardware-software co-validation, this part offers sufficient capacity for typical 32-bit SoC subsets and image-processing pipelines.
Recommended
Digital Video Broadcast / Image Processing
The 192 dedicated 18x18 multipliers enable real-time HD video filtering, scaling, and deinterlacing in the EP1S60F1020C6NAA. TriMatrix memory provides line buffers, frame buffers, and chroma upsampling FIFOs without external SDRAM in many designs. The 773 user I/O can drive parallel RGB/YCbCr interfaces plus a downstream HDMI/DVI encoder. The C6 speed grade sustains 150 MHz pixel clocks, sufficient for 1080p60 with 24-bit color depth. Power consumption at full utilization is approximately 6-10 W requiring careful PCB thermal design.
Recommended
Test and Measurement Instrumentation
Engineers build pattern generators, protocol analyzers, and logic-state-capture instruments around the EP1S60F1020C6NAA because of its combination of high logic density, ample block RAM, and parallel I/O. The 773 I/O banks can sample or drive 100+ channels at 100 MHz while the TriMatrix memory buffers deep capture traces. Multiple PLLs synthesize independent test rates. Its 1.5V VCCINT core, MultiVolt I/O, and JTAG configuration simplify integration with commercial test platforms and existing DUT boards.
Recommended
Industrial High-Speed Control
In motion-control, industrial-automation, and high-speed encoder interface designs, the EP1S60F1020C6NAA provides the determinism and parallel DSP performance required for multi-axis servo loops. The hardware multipliers execute PID, FOC, and field-weakening algorithms in hardware, while 5 Mbit of block RAM buffers encoder captures and trajectory tables. The 773 I/O directly interface to differential quadrature encoders, PWM outputs, and isolated digital I/O. Industrial-grade temperature variants (EP1S60F1020I6) extend operating range to -40C to +100C.
Recommended
Recommended Products Summary
Engineering reference data for EP1S60F1020C6NAA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S60F1020C6N | EP1S60F1020C6 | EP1S60F1020C5N | EP1S60F1020C5 |
|---|---|---|---|---|---|
| Package | 1020-BBGA | 1020-BBGA - same | 1020-BBGA - same | 1020-BBGA - same | 1020-BBGA - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Logic Elements | 57,120 | 57,120 - same | 57,120 - same | 57,120 - same | 57,120 - same |
| Total RAM Bits | 5,215,104 | 5,215,104 - same | 5,215,104 - same | 5,215,104 - same | 5,215,104 - same |
| Maximum User I/O | 773 | 773 - same | 773 - same | 773 - same | 773 - same |
| Speed Grade | C6 (-2) | C6 - same | C6 - same | C5 (-1, faster) | C5 (-1, faster) |
| Lead-Free / RoHS | Yes (N) | Yes | No (SnPb) | Yes | No (SnPb) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Customer-specific 'AA' trim code (vs EP1S60F1020C6N)
- Balanced speed-grade performance (vs EP1S60F1020C5N)
- Largest I/O count of EP1S60 family (vs EP1S60B956C6 (956-BBGA))
Design Notes
Estimated: Power dissipation at full logic utilization with 50 MHz toggle rate is approximately 6-10 W for the EP1S60F1020C6NAA. At 85C ambient the junction temperature must stay below 150C; thermal resistance theta_JA is approximately 8 C/W for the 1020-BGA with JEDEC EIA/JESD51 test board. Provide a top-side heatsink or thermal pad in addition to multi-layer ground/power planes. Voltage sequencing is mandatory: VCCINT (1.5V) first, then VCCAUX (1.5V/1.8V), then VCCIO banks. Hot-swap is NOT supported on this family.
The 1020-BGA at 1.0 mm pitch requires an HDI PCB stackup with at least six layers. Use 4 mil trace width with 4 mil spacing and a microvia-in-pad design to escape the inner ball rows. Place decoupling capacitors on the opposite PCB side directly under their corresponding BGA balls with short via stubs. Per the Stratix device handbook, use 1 uF X7R for high-frequency decoupling and 47 uF bulk per VCCIO bank. Ensure the JTAG header is accessible for factory programming and field updates.
Common pitfalls: (1) Using unsupported Quartus versions (use Quartus II 9.0-13.1 for legacy Stratix support); (2) Forgetting the configuration-mode MSEL pull-up/pull-down resistors per the selected scheme (Fast Passive Parallel vs Passive Serial); (3) Crossing VCCIO banks with incompatible I/O standards without buffer logic; (4) Driving LVDS without the 100-ohm differential termination; (5) Assuming EP1S60 EPROM-style configuration - this family is SRAM-based and requires a configuration PROM (EPCS16/EPCS64) or flash at every power-up.
For LVDS or LVDS-extended I/O, route traces with 100-ohm differential impedance and keep intra-pair skew below 20 ps. The Stratix handbook recommends matched length within a bank of 100 mils maximum; in practice use length-matched Serpentine routing from FPGA ball to connector. For 6.5 Gbps transceivers, isolate the analog supply plane from digital noise using a ferrite bead and a separate filter network. Reference the Stratix Transceiver Handbook for full PCB stackup guidance.
Compliance Information
RoHS compliant per Altera 'N' suffix marking. REACH SVHC compliance is unknown because Altera has not re-tested this obsolete part against current SVHC lists. AEC-Q100 not applicable (commercial-grade FPGA). Halogen-free status not stated on legacy datasheet.
