EP1S80B956C6AB - Stratix 79K LE FPGA, 956-BGA | Intel
MPN: EP1S80B956C6AB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $142 | $142,000.00 |
Drop-in alternatives for EP1S80B956C6AB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1S80B956C6
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View Datasheet →EP1S80B956C6AA
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View Datasheet →EP1S60B956C6
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View Datasheet →EP1S80B956C5N
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View Datasheet →EP1S80B956C6AB Maximum Ratings & Electrical Characteristics
| Family | Stratix |
| Logic Elements (LEs) | 79,040 |
| Logic Cells | 79,040 |
| Process Technology | 130 nm |
| Core Voltage | 1.5 V |
| Maximum Operating Frequency | 450.05 MHz |
| User I/O Pins | 683 |
| Package | 956-ball FCBGA |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Memory Blocks | TriMatrix embedded RAM |
| DSP Blocks | Embedded DSP blocks (per Stratix family) |
| PLLs | Multiple PLLs for clock management |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial |
| Manufacturer | Intel (formerly Altera) |
EP1S80B956C6AB 956-ball fcbga Pin Configuration Guide
Complete pinout information for EP1S80B956C6AB (956-ball fcbga package) with 683 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1S80B956C6AB.
Refer to the datasheet for full pin configuration.
Estimated pin count: 683 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S80B956C6AB is suitable for 6 applications: Telecom Baseband Processing, ASIC Prototyping, High-Speed Data Acquisition Systems, Image and Video Processing, Industrial Control and Motor Drive, Military and Aerospace Avionics.
Telecom Baseband Processing
The EP1S80B956C6AB is well-suited for telecom baseband signal processing because its 79,040 logic elements plus embedded DSP blocks can implement parallel FIR filters, channelizers, and forward error correction in a single device. With 683 user I/Os the FPGA can connect to multiple ADC/DAC lanes, external SRAM/RLDRAM buffers, and CPRI/OBSAI framer interfaces. Operating at a 1.5 V core with up to 450 MHz fabric, designers can hit the throughput required for multi-antenna 3G/4G base station channel cards. The 956-BGA footprint provides the signal integrity needed for LVDS and HSTL memory interfaces used in symbol-rate processing, making this part historically common in wireless infrastructure designs.
Recommended
ASIC Prototyping
ASIC prototyping is a primary use case for the EP1S80B956C6AB because 79,040 LEs can emulate complex multi-million-gate ASICs at hardware speed, enabling pre-silicon software development and system validation. The TriMatrix memory and embedded DSP blocks replicate common ASIC compute primitives, while 683 I/Os let engineers break a design across multiple FPGAs via high-speed serial or parallel bridges. Designers compile ASIC RTL into Quartus II and partition the design across EP1S80 devices for FPGA-based prototyping. Reference: Altera ASIC Pro design flow documentation.
Recommended
High-Speed Data Acquisition Systems
The EP1S80B956C6AB fits high-speed data acquisition systems because its 683 user I/Os can sink multiple parallel ADC lanes, and embedded DSP blocks perform decimation, FFT, and channel filtering in real time. Designers can pair this device with 14-/16-bit ADCs running at 100-200 MSPS and process multi-channel data inside the FPGA fabric before forwarding via external memory or Ethernet. The 1.5 V core plus per-bank VCCIO supports mixed LVDS/LVCMOS interfaces to ADCs and DACs. Reference: Altera reference designs for radar and test-and-measurement front-ends.
Recommended
Image and Video Processing
The EP1S80B956C6AB supports image and video processing pipelines because its DSP blocks implement convolution, motion estimation, and color-space conversion at real-time rates, and its memory bandwidth handles full-HD frame buffers. With 79,040 LEs and embedded RAM, the FPGA can drive HDMI/DVI input-output, perform deinterlacing, scaling, and overlay, and feed compressed streams to external encoders. Reference: Altera video reference designs for broadcast and surveillance. The 956-BGA package provides enough I/O for parallel video buses, and 1.5 V core operation gives low power per video channel.
Recommended
Industrial Control and Motor Drive
Industrial control and motor drive applications benefit from the EP1S80B956C6AB's 79,040 LEs and 683 I/Os, which can host multi-axis motion controllers, encoder interfaces (EnDat, BISS, SSI), and fieldbus bridges (EtherCAT, PROFINET) simultaneously. Designers implement current/torque loops in hardware DSP blocks for deterministic sub-microsecond response, while the high pin count supports parallel GPIO for limit switches, brake drivers, and resolver excitation. The 1.5 V core with industrial temperature grade (per datasheet ordering suffix) operates reliably in factory environments.
Recommended
Military and Aerospace Avionics
Military and aerospace avionics historically deploy the EP1S80B956C6AB for radar, electronic warfare, and secure communications because high-density FPGAs with hardware-level parallelism deliver deterministic latency impossible on processors. The 956-BGA FCBGA supports ruggedized PCB stack-ups, and the Stratix family offers extended-temperature and military-qualified ordering codes. Designers implement FFT-based signal detection, cryptographic primitives, and protocol bridges on a single device. Reference: Altera/Intel military and aerospace product briefs for original Stratix.
Recommended
Recommended Products Summary
Engineering reference data for EP1S80B956C6AB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S80B956C6 | EP1S80B956C6AA | EP1S60B956C6 | EP1S80B956C5N |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 956-BGA (FCBGA) | 956-BGA (FCBGA) - same | 956-BGA (FCBGA) - same | 956-BGA (FCBGA) - same | 956-BGA (FCBGA) - same |
| Logic Elements | 79,040 LEs | 79,040 LEs | 79,040 LEs | 57,120 LEs (-28%) | 79,040 LEs |
| Process Technology | 130 nm | 130 nm | 130 nm | 130 nm | 130 nm |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| User I/O Pins | 683 | 683 | 683 | [DATA_NEEDED] | 683 |
| Maximum Operating Frequency | 450.05 MHz | 450.05 MHz | 450.05 MHz | 450.05 MHz | [DATA_NEEDED: C5 is slower speed grade] |
| Speed Grade | C6 | C6 (same) | C6 + AA suffix | C6 | C5 (slower) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Family | Stratix | Stratix | Stratix | Stratix | Stratix |
Key Differentiators
- Pin-compatible with 956-BGA family members for flexible sourcing (vs EP1S60B956C6)
- High pin-count 956-BGA supports 683 I/Os (vs EP1S80B956C5N)
- Legacy Altera/Intel design ecosystem support (vs Generic FPGAs)
Design Notes
Estimated: at typical Stratix core utilization of 70% and 200 MHz toggle rate, the EP1S80B956C6AB dissipates 6-10 W; design the 956-BGA PCB with a thermal pad soldered to a large inner-plane copper pour (minimum 4 sq inches) to keep junction temperature below 100 °C. Reference: Altera Stratix PowerPlay early power estimator guidelines.
The 956-BGA package has 1.0 mm pitch typical for Stratix FCBGA. Use microvia or stacked-via PCB technology and follow Altera's BGA escape routing guidelines. Place decoupling capacitors within 100 mil of every VCC pin and use a power-plane island beneath the BGA. Reference: Altera Stratix Hardware Reference Design Guidelines.
Do not migrate the EP1S80B956C6AB design to a Stratix II device (EP2S series) without a full PCB redesign because the Stratix II BGA pinout is not pin-compatible. Verify Quartus II version supports the original Stratix family: only legacy Quartus II (up to v9.x for Stratix I) compiles EP1S designs; newer Quartus versions reject this family.
Differential pairs (LVDS) on the EP1S80B956C6AB require matched-length routing within 50 mil and 100 ohm differential impedance. Use IBIS models from Intel/Altera for SI simulation. Reference: Altera Stratix Device Handbook, LVDS chapter.
Compliance Information
RoHS compliant per distributor listings (Arrow). AEC-Q100 not applicable - this is a commercial/industrial FPGA. Lead-free per datasheet. Halogen-free status unknown from provided data.
