EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel
MPN: EPM7128SLI84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $8.4 | $8,400.00 |
Drop-in alternatives for EPM7128SLI84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SLI84-10N
β Drop-Inβ In Stock
$8.45 / Unit
View Datasheet βEPM7128SLC84-15
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEPM7128SLC84-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLI84-10
β Drop-Inβ In Stock
$7.25 / Unit
View Datasheet βEPM7128SLC84-10
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM7128SLI84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Series | EPM7128S |
| Device Type | EE PLD (CPLD) |
| Macrocells | 128 |
| Logic Elements | 250 (approx.) |
| User I/O Pins | 84 (68 in 84-pin PLCC per some sources) |
| Propagation Delay (tpd) | 15 ns |
| Supply Voltage (VCCINT) | 4.5 V to 5.5 V |
| I/O Voltage Tolerance | 3.3 V or 5.0 V (configurable) |
| Process Technology | CMOS EEPROM |
| Program Memory Type | EEPROM (in-system programmable) |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Operating Temperature | -40 C to +85 C (Industrial grade, 'I' suffix) |
| Pin Count | 84 |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) |
| Maximum User Flash Endurance | 100 program/erase cycles |
| Data Retention | 20 years |
EPM7128SLI84-15 Pin Configuration
| Pin 1 | I/O β User I/O - global clock option (GCLK1) |
| Pin 2 | I/O β User I/O |
| Pin 3 | I/O β User I/O |
| Pin 4 | I/O β User I/O |
| Pin 5 | I/O β User I/O |
| Pin 6 | I/O β User I/O |
| Pin 7 | I/O β User I/O |
| Pin 8 | I/O β User I/O |
| Pin 9 | I/O β User I/O |
| Pin 10 | I/O β User I/O |
| Pin 11 | I/O β User I/O |
| Pin 12 | I/O β User I/O |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O |
| Pin 15 | I/O β User I/O |
| Pin 16 | I/O β User I/O |
| Pin 17 | I/O β User I/O |
| Pin 18 | I/O β User I/O |
| Pin 19 | I/O β User I/O |
| Pin 20 | I/O β User I/O |
| Pin 21 | I/O β User I/O |
| Pin 22 | I/O β User I/O |
| Pin 23 | I/O β User I/O |
| Pin 24 | I/O β User I/O |
| Pin 25 | I/O β User I/O |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O |
| Pin 28 | I/O β User I/O |
| Pin 29 | I/O β User I/O |
| Pin 30 | I/O β User I/O |
| Pin 31 | I/O β User I/O |
| Pin 32 | I/O β User I/O |
| Pin 33 | I/O β User I/O |
| Pin 34 | I/O β User I/O |
| Pin 35 | I/O β User I/O |
| Pin 36 | I/O β User I/O |
| Pin 37 | I/O β User I/O |
| Pin 38 | I/O β User I/O |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O |
| Pin 41 | I/O β User I/O |
| Pin 42 | I/O β User I/O |
| Pin 43 | I/O β User I/O |
| Pin 44 | TDI β JTAG Test Data In |
| Pin 45 | I/O β User I/O |
| Pin 46 | I/O β User I/O |
| Pin 47 | I/O β User I/O |
| Pin 48 | I/O β User I/O |
| Pin 49 | I/O β User I/O |
| Pin 50 | I/O β User I/O |
| Pin 51 | I/O β User I/O |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O |
| Pin 54 | I/O β User I/O |
| Pin 55 | I/O β User I/O |
| Pin 56 | I/O β User I/O |
| Pin 57 | I/O β User I/O |
| Pin 58 | I/O β User I/O |
| Pin 59 | I/O β User I/O |
| Pin 60 | I/O β User I/O |
| Pin 61 | I/O β User I/O |
| Pin 62 | I/O β User I/O |
| Pin 63 | I/O β User I/O |
| Pin 64 | I/O β User I/O |
| Pin 65 | GND β Ground |
| Pin 66 | I/O β User I/O |
| Pin 67 | I/O β User I/O |
| Pin 68 | I/O β User I/O |
| Pin 69 | I/O β User I/O |
| Pin 70 | TMS β JTAG Test Mode Select |
| Pin 71 | I/O β User I/O |
| Pin 72 | I/O β User I/O |
| Pin 73 | I/O β User I/O |
| Pin 74 | I/O β User I/O |
| Pin 75 | I/O β User I/O |
| Pin 76 | I/O β User I/O |
| Pin 77 | I/O β User I/O |
| Pin 78 | GND β Ground |
| Pin 79 | I/O β User I/O |
| Pin 80 | TCK β JTAG Test Clock |
| Pin 81 | I/O β User I/O |
| Pin 82 | I/O β User I/O |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | VCC β 5 V supply (VCCINT) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SLI84-15 is suitable for 6 applications: Microprocessor Bus Address Decoding, Industrial Control and Automation, Peripheral Interface Bridging, Legacy Telecom Backplane Glue Logic, PCB Redesign and Field-Replaceable Logic, Test and Measurement Instrumentation.
Microprocessor Bus Address Decoding
The EPM7128SLI84-15 fits microprocessor bus address decoding because its 128 macrocells and 84 PLCC pins can implement multi-bank chip-select decoders for legacy 16- and 32-bit busses without external AND/OR gates. With 15 ns tpd the part reliably registers between an Intel 8086/80286 bus cycle and peripheral access time, even at industrial temperature. Use the JTAG port for in-system updates to the decoder map, eliminating the need to swap PROMs or PALs when a peripheral changes. Compared to discrete 74LS/74F glue logic, a single CPLD consolidates address decoding, chip-select generation, and wait-state insertion in one reprogrammable device.
Recommended
Industrial Control and Automation
In industrial automation the EPM7128SLI84-15 functions as a deterministic state-machine controller for PLC backplanes, motor control boards, and HMI panels. Its instant-on EEPROM eliminates FPGA configuration delays, ensuring deterministic boot-time behavior in safety-critical loops. The industrial temperature grade (-40 C to +85 C) plus 5 V I/O tolerance handles the harsh EMI and voltage transients typical of factory-floor environments. With 128 macrocells the part can implement multi-axis sequencing, encoder decoding, and PID timing in one device, replacing several discrete timers and counters.
Recommended
Peripheral Interface Bridging
The EPM7128SLI84-15 is well-suited to bridge incompatible peripheral interfaces such as ISA-to-PCI, parallel-port-to-memory, or 5 V TTL to 3.3 V CMOS logic. With 84 user I/O pins the part can run a full 32-bit data bus plus control signals concurrently, and the configurable 3.3 V/5 V I/O banks allow direct level translation without external buffers. The 15 ns tpd meets ISA-bus timing (250 ns cycle) with comfortable margin while the EEPROM-based design retains configuration through power cycles, eliminating boot PROMs.
Recommended
Legacy Telecom Backplane Glue Logic
The EPM7128SLI84-15 serves telecom backplane designs where multi-drop TDM buses, parallel data paths, and control signaling must be aggregated without timing ambiguity. Its deterministic 15 ns propagation and 84 I/O pins are ideal for parallel-to-serial conversion, framing, and clock distribution in T1/E1 multiplexer boards. The 5 V tolerance supports legacy line-card interfaces, and the -40 C to +85 C industrial grade meets NEBS thermal requirements. Use the JTAG boundary-scan to verify interconnect during board bring-up and field service.
Recommended
PCB Redesign and Field-Replaceable Logic
When an existing PCB needs a logic change after fab, replacing discrete TTL/CMOS gates with the EPM7128SLI84-15 is an effective path: it consolidates 5-10 small packages into one PLCC-84 socket, leaves the I/O pinout identical, and lets the engineer rewrite logic via JTAG. The non-volatile EEPROM means no external boot PROM is needed and the design can be field-upgraded with a JTAG programmer. With 128 macrocells the part can absorb most glue-logic changes without resorting to a larger CPLD.
Recommended
Test and Measurement Instrumentation
The EPM7128SLI84-15 is widely used in test-and-measurement front-ends to generate timing sequences, gate triggers, and address multiplexers for data-acquisition cards. Its 15 ns tpd comfortably generates pulse trains at 5-10 MHz for general-purpose stimulus, and 84 I/O pins support wide parallel stimulus buses. The 5 V tolerance interfaces directly with TTL comparators and precision ADCs (e.g. AD9220, ADS805), and the JTAG port enables remote logic updates in deployed test systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SLI84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SLI84-10N | EPM7128SLC84-15 | EPM7128SLC84-15N | EPM7128SLI84-10 | EPM7128SLC84-10 |
|---|---|---|---|---|---|---|
| Package | PLCC-84 (J-lead) | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tpd) | 15 ns | 10 ns (faster) | 15 ns | 15 ns | 10 ns (faster) | 10 ns (faster) |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) |
| Pb-free Finish (N suffix) | No (SnPb finish) | Yes | No | Yes | No | No |
| Architecture | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| I/O Standards | 3.3 V / 5 V configurable | 3.3 V / 5 V configurable | 3.3 V / 5 V configurable | 3.3 V / 5 V configurable | 3.3 V / 5 V configurable | 3.3 V / 5 V configurable |
Key Differentiators
- Largest macrocell density in MAX 7000S family (vs EPM7064SLC44 (smaller MAX 7000S member))
- 15 ns tpd at industrial temperature grade (vs EPM7128SLC84-15 (commercial temperature))
- In-system reprogrammable EEPROM (vs Discrete 74LS/74F TTL glue logic)
Design Notes
The EPM7128SLI84-15 PLCC-84 socket should be a low-profile through-hole type if field upgrades are expected (Altera recommends AMP 1-822473-1 or equivalent). Place at least four 0.1 uF decoupling capacitors near the VCCINT pins (1, 13, 26, 39, 52, 65, 78) and tie all GND pins to a continuous ground plane. Keep JTAG pins (TDI/TDO/TMS/TCK) away from high-speed clocks to avoid noise injection during boundary-scan testing.
Use series termination (33-68 ohm) on high-speed outputs (>50 MHz toggle rate) to dampen reflections on PLCC-84 stub traces. Configure I/O pins as slow-slew-rate when driving capacitive loads to reduce ground bounce. Avoid routing adjacent I/O pins as differential pairs without ground shielding, since PLCC-84 has higher mutual inductance than TQFP packages.
Do not confuse the EPM7128SLI84-15 (MAX 7000S, requires Altera MasterBlaster/ByteBlaster programmer) with the EPM7128ELI84-20 (MAX 7000E, supports JTAG ISP). Both share the same PLCC-84 pinout but use different programming flows - the S variant needs an external programmer while the E variant uses JTAG. Verify the BSDL file matches the specific die revision when designing boundary-scan tests.
Compliance Information
Original Altera/Intel MAX 7000 family parts (pre-2006) were typically Pb-containing finishes. RoHS/REACH compliance is unknown for this specific lot; consult the lot date code and original shipping documentation. Not AEC-Q100 qualified (industrial-grade, not automotive).
